公开(公告)号：US3868723A

公开(公告)日：1975-02-25

申请号：US42426773

申请日：1973-12-13

Applicant: IBM

Inventor： LECHATON JOHN S ,  RICHARD LEO P ,  SMITH DARYL C

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/06 ,  H01L29/49 ,  H01L11/00 ,  H01L15/00

CPC classification number: H01L29/4966 ,  H01L21/76819 ,  H01L23/5226 ,  H01L29/0638 ,  H01L29/495 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method of partially planarizing an electrically insulative layer over an integrated circuit substrate which has a raised line metallization pattern having narrower lines and wider lines. The insulative layer has narrower and wider elevations corresponding to the underlying lines. Resputtering of said insulative layer is conducted for an amount of time sufficient to planarize the narrower elevations in the layer but insufficient to so planarize its wider elevations. This method is useful in planarizing insulative layer elevations through which via holes are to be formed, particularly via holes which are wider than the underlying metallizing lines which they contact. Such a planarization method in via hole formation avoids the tunneling effects which would otherwise result from the over-chemical etching necessary to form the via holes.

Abstract translation: 一种在集成电路基板上部分平坦化电绝缘层的方法，所述集成电路基板具有具有窄线和宽线的凸起线金属化图案。 绝缘层具有对应于底层线的较窄和较宽的高度。 进行所述绝缘层的再溅射一段时间，足以平坦化层中较窄的高度，但不足以平坦化其较高的高度。 该方法可用于平坦化通过其形成通孔的绝缘层高度，特别是通孔比它们接触的下面的金属化线更宽。 通孔形成中的这种平面化方法避免了由形成通孔所必需的过度化学蚀刻而导致的隧道效应。

公开(公告)号：US3664942A

公开(公告)日：1972-05-23

申请号：US3664942D

申请日：1970-12-31

Applicant: IBM

Inventor： HAVAS JANOS ,  LECHATON JOHN S

IPC: C23F4/00 ,  H01J37/32 ,  C23C15/00

CPC classification number: H01J37/32935 ,  C23F4/00

Abstract: The end point in sputter-etching metal layers, for example, from substrates is determined by employing a silicon, quartz, or the like, monitor control wafer in the sputter-etching environment which wafer has been previously coated with said metal, for example, in the same run as that used to fabricate the workpiece substrate. Thus, the monitor control wafer exhibits the same thickness of metal, or the like, as the thickness of the metal layer to be selectively sputter-etched from the substrate. The temperature exhibited by the monitor control wafer during the sputter-etching material removal process in monitored by an infrared radiation thermometer, by way of a quartz window. When the layer of metal, or the like, has been removed from the monitor control wafer, the temperature, as sensed by the infrared radiation thermometer during sputter-etching, declines thereby indicating the end point in the removal process of the metal layer, or the like.

Abstract translation: 例如通过采用硅，石英等在溅射蚀刻金属层中的溅射蚀刻金属层中的终点，通过采用硅，石英等来监测晶片已经预先用所述金属涂覆的溅射蚀刻环境中的控制晶片， 与用于制造工件基板的操作相同。 因此，作为要从基板选择性地溅射蚀刻的金属层的厚度，监视器控制晶片呈现相同厚度的金属等。 在溅射蚀刻材料去除过程期间由监测控制晶片呈现的温度由红外辐射温度计通过石英窗监测。 当已经从监视器控制晶片去除了金属层等时，在溅射蚀刻期间由红外辐射温度计感测到的温度下降，从而表明金属层的去除过程中的终点，或 类似。

公开(公告)号：DE3784117T2

公开(公告)日：1993-08-12

申请号：DE3784117

申请日：1987-07-14

Applicant: IBM

Inventor： BONDUR JAMES ALLAN ,  GIAMMARCO NICHOLAS JAMES ,  HANSEN THOMAS ADRIAN ,  KAPLITA GEORGE ANTHONY ,  LECHATON JOHN S

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/263

Abstract: Disclosed is a process for etching semiconductor materials with a high etch rate against an insulator mask using a novel etchant gas mixture. The mixture consists of a fluorochlorohydrocarbon (e.g., CCl2F2, CHCl2F2, CCl4 or CCl3F), SF6, O2 and an inert gas (e.g. He). The preferred gas mixture contains 2/1 ratio of the fluorochlorocarbon to SF6 and the following composition: 1-4 % of SF6, 3-10 % of O2, 74-93 % of He and 3-10 % of fluorochlorohydrocarbon. The etch rate of silicon (or silicide) against an oxide mask using this etchant gas mixture under normal etching conditions is high, on the order of 30-40. An impressive feature of the process is shape control of trenches by mere manipulation of the RIE system power.

公开(公告)号：DE3467472D1

公开(公告)日：1987-12-17

申请号：DE3467472

申请日：1984-08-08

Applicant: IBM

Inventor： LECHATON JOHN S ,  PITNER PHILIP MICHAEL ,  SRINIVASAN GURUMAKONDA RAMASAM

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L21/00 ,  H01L29/72

Abstract: A high performance NPN bipolar transistor functioning in a current switch logic circuit is formed within an isolated region of a monocrystalline silicon body (10) wherein the transistor includes an N+ subcollector (12), an N+ collector reach-through (20) which connects the subcollector to a major surface of the silicon body, a P base region (22) above the subcollector and adjacent to the reach-through region, an N+ emitter region (30) within the base region and extending from the major surface. The base region (22) includes intrinsic base region located below the emitter region (30) and an extrinsic region (34) located extending from the major surface and adjacent to the emitter region. The extrinsic base preferably completely surrounds or rings the emitter region. Using a mask (32) with openings (24) only in the areas of the extrinsic base regions a P+ type region (34) is formed by ion implanting with a P type dopant to a depth of less than the depth of the N emitter region (30) followed by a short thermal anneal to activate the P dopant. By the independent control of the intrinsic and extrinsic base resistances the performance of bipolar transistor integrated circuits for current switch logic applications is substantially increased.

公开(公告)号：DE2709933A1

公开(公告)日：1977-11-17

申请号：DE2709933

申请日：1977-03-08

Applicant: IBM

Inventor： FENG BAI CWO ,  LECHATON JOHN S

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  H01L21/283 ,  H01L21/26

Abstract: A method for forming feedthrough connections, or via studs, between levels of metallization atop semiconductor substrates. A first level conductive pattern is formed atop the substrate. A feedthrough pattern is then formed atop the first conductive pattern, the feedthrough pattern including one or more metal studs and a second, expendable material disposed on the studs. The formation of the feedthrough pattern is preferably accomplished by a lift-off process. The expendable material is removable by an etchant which does not substantially attack either the metal or the substrate. An insulator is deposited atop the substrate and the pattern by RF sputtering at a bias which is sufficiently high to cause substantial reemission of the insulator, thereby covering the exposed substrate surfaces and the expendable material but leaving the side surfaces of the material exposed. The expendable material is then etched with said etchant, thereby removing the second material and the portion of the insulator disposed thereon. A second conductive pattern may then be formed atop the insulator and selectively connected to the feedthroughs which thereby provide the interconnection between the first and second levels.

公开(公告)号：CA2024640C

公开(公告)日：1993-07-27

申请号：CA2024640

申请日：1990-09-05

Applicant: IBM

Inventor： LECHATON JOHN S ,  SCHEPIS DOMINIC J

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/336

Abstract: A BiCMOS PROCESS of the Invention A method for manufacturing a BiCMOS device includes providing a semiconductor substrate including first and second electrically isolated device regions. A layer of insulating material is formed over the first device region, and a layer of conductive material is formed conformally over the device. Portions of the conductive layer are removed to leave a base contact on the surface of the second device region and an insulated gate contact over the surface of the first device region. A FET is formed in the first device region having a channel under the insulated gate. A vertical bipolar transistor is formed in the second device region having a base region contacting the base contact.

公开(公告)号：DE3162991D1

公开(公告)日：1984-05-10

申请号：DE3162991

申请日：1981-10-29

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  LECHATON JOHN S ,  WALSH JAMES LEO

IPC: C01B33/12 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/312 ,  H01L21/76 ,  H01L21/31

公开(公告)号：CA1044378A

公开(公告)日：1978-12-12

申请号：CA298325

申请日：1978-03-20

Applicant: IBM

Inventor： LECHATON JOHN S ,  RICHARD LEO P ,  SMITH DARYL C

IPC: H01L21/203

Abstract: PARTIAL PLANARIZATION OF ELECTRICALLY INSULATIVE FILMS BY RESPUTTERING A method of partially planarizing an electrically insulative layer over an integrated circuit substrate which has a raised line metallization pattern having narrower lines and wider lines. The insulative layer has narrower and wider elevations corresponding to the underlying lines. Resputtering of said insulative layer is conducted for an amount of time sufficient to planarize the narrower elevations in the layer but insufficient to so planarize its wider elevations. This method is useful in planarizing insulative layer elevations through which via holes are to be formed, particularly via holes which are wider than the underlying metallizing lines which they contact. Such a planarization method in via hole formation avoids the tunneling effects which would otherwise result from the over-chemical etching necessary to form the via holes.

公开(公告)号：FR2349957A1

公开(公告)日：1977-11-25

申请号：FR7706018

申请日：1977-02-24

Applicant: IBM

Inventor： FENG BAI C ,  LECHATON JOHN S

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  H01L21/90 ,  H01L23/52

Abstract: A method for forming feedthrough connections, or via studs, between levels of metallization atop semiconductor substrates. A first level conductive pattern is formed atop the substrate. A feedthrough pattern is then formed atop the first conductive pattern, the feedthrough pattern including one or more metal studs and a second, expendable material disposed on the studs. The formation of the feedthrough pattern is preferably accomplished by a lift-off process. The expendable material is removable by an etchant which does not substantially attack either the metal or the substrate. An insulator is deposited atop the substrate and the pattern by RF sputtering at a bias which is sufficiently high to cause substantial reemission of the insulator, thereby covering the exposed substrate surfaces and the expendable material but leaving the side surfaces of the material exposed. The expendable material is then etched with said etchant, thereby removing the second material and the portion of the insulator disposed thereon. A second conductive pattern may then be formed atop the insulator and selectively connected to the feedthroughs which thereby provide the interconnection between the first and second levels.

公开(公告)号：DE3380583D1

公开(公告)日：1989-10-19

申请号：DE3380583

申请日：1983-02-23

Applicant: IBM

Inventor： GAUR SANTOSH PRASAD ,  LECHATON JOHN S ,  SRINIVASAN GURUMAKONDA R

IPC: H01L29/73 ,  H01L21/3065 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/72

Abstract: A process is described which permits the fabrication of very narrow base width bipolar transistors. The ability to selectively vary the transistor characteristics provides a degree of freedom for design of integrated circuits. The biplar transistor is processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, a portion of the base area (22) wherein the emitter region (34) is planned to be formed is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers (24, 26) with the emitter opening (30) therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization. Since the intrinsic base under the emitter (34) is etched, and the normal emitter is formed afterwards, the etching reduces the base width by an amount approximately equal to the etched depth. The transistor characteristics depend strongly upon the base width so the etching is controlled to very tight dimensions.