公开(公告)号：WO2015032274A9

公开(公告)日：2016-03-24

申请号：PCT/CN2014084756

申请日：2014-08-20

Applicant: IBM ,  IBM CHINA CO LTD

Inventor： NACZAS SEBASTIAN ,  PARUCHURI VAMSI ,  REZNICEK ALEXANDER ,  SCHEPIS DOMINIC J

IPC: H01L29/78

CPC classification number: H01L23/535 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region.

Abstract translation: 可以通过形成在其上形成这种接触的无缺陷表面来实现对finFET源极/漏极的低电阻接触。 finFET的翅片可以暴露于外延生长条件以增加源极/漏极中的半导体材料的体积。 面对增长的前沿可以合并或形成未成熟的方面。 电介质材料可以填充源极漏极区域内的空隙。 与finFET栅极隔开的沟槽可以暴露在所述沟槽内的鳍片上的刻面外延生长的顶部，这些顶部由光滑电介质表面分开。 选择性地形成在暴露在沟槽内的顶部上的硅层可以转化为半导体金属层，将这种接触与源极漏极区域中的各个鳍连接。

公开(公告)号：JP2004193596A

公开(公告)日：2004-07-08

申请号：JP2003396240

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DORIS BRUCE B ,  CHIDAMBARRAO DURESETI ,  BAIE XAVIER ,  MANDELMAN JACK A ,  SADANA DEVENDRA K ,  SCHEPIS DOMINIC J

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78696

Abstract: PROBLEM TO BE SOLVED: To provide a field-effect transistor whose charge carrier mobility increases by the stress of an electric current channel 22.
SOLUTION: The direction of the stress is that in which a current flows (vertical direction). For a PFET device, the stress is compressive stress, while the stress is tensile stress in an NFET device. The stress is produced by a compressive film 34 located in an area 32 under the channel. The compressive film pushes up the channel 22 which bends the channel. In the PFET device, the compressive film is arranged under the edge 31 of the channel (e.g., under a source or drain) which compresses the upper part 22A of the channel. In the NFET device, the compressive film is arranged under the center 40 of the channel (e.g., under the gate) which pulls the upper part 22A of the channel. Therefore, both the NFET device and the PFET device can be strengthened. A method for manufacturing these devices is included.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2000223684A

公开(公告)日：2000-08-11

申请号：JP2000017676

申请日：2000-01-26

Applicant: IBM

Inventor： AJMERA ATUL ,  LEOBANDUNG EFFENDI ,  RAUSCH WERNER ,  SCHEPIS DOMINIC J ,  SHAHIDI GHAVAM G

IPC: H01L27/12 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L23/52 ,  H01L23/58 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a substrate contact in a substrate with a silicon-on-insulator region. SOLUTION: A shallow isolation trench is formed in a silicon-on-insulator. The shallow isolation trench is filled. A photoresist is glued onto a substrate. A contact trench is formed in the substrate through the filled, shallow isolation trench, the silicon-on-insulator, and a silicon substrate 3 at the lower side of the silicon-on-insulator. The contact trench is filled, a material 21 for filling the contact trench forms a contact to the silicon substrate 3, and grounds the substrate 3, thus solving the problem of the accumulation of static charge in the substrate 3.

公开(公告)号：JP2001274343A

公开(公告)日：2001-10-05

申请号：JP2001048615

申请日：2001-02-23

Applicant: IBM

Inventor： GAUTHIER JR ROBERT J ,  SCHEPIS DOMINIC J ,  TONTI WILLIAM R ,  VOLDMAN STEVEN H

IPC: H01L27/04 ,  H01L21/762 ,  H01L21/763 ,  H01L21/822 ,  H01L23/367 ,  H01L27/00 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure wherein the thermal conductivity is enhanced, and its manufacturing method. SOLUTION: During manufacturing of selected electronic components, silicon is formed at selected position on a substrate. Dielectric isolation regions are formed in an upper silicon layer and filled with a thermal conductive material. Before depositing the thermal conductive material, a liner material may be deposited at option. In a second embodiment, a horizontal layer of the thermal conductive material is deposited in an oxide layer or bulk silicon layer beneath the upper silicon layer.

公开(公告)号：JP2001244477A

公开(公告)日：2001-09-07

申请号：JP2001017463

申请日：2001-01-25

Applicant: IBM

Inventor： SCOTT CLAUDER ,  SCHEPIS DOMINIC J ,  MELANIE J SHERONY

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a semiconductor device having an SOI structure operating by improved performance compared to a conventional SOI device, by forming a junction leaking path which consistently and effectively diffuses a main body charge during the operation of the device in the source area and the drain area of SOI structure. SOLUTION: The semiconductor device of SOI structure has a source area and a drain area, which are formed by injecting silicon or germanium ions in a silicon layer and which are made to be amorphous. The completely amorphous source area and the drain area, bring permanent crystal defects and diffuse a charge in a device main body. Thus, the leak of a p-n junction improving the whole efficiency and performance of the device is generated.

公开(公告)号：JP2004214628A

公开(公告)日：2004-07-29

申请号：JP2003396341

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HIIMYONGU PAAKU ,  LEE BYOUNG H ,  PAUL D AGUNERO ,  SCHEPIS DOMINIC J ,  SHAHIDI GHAVAM G

IPC: H01L21/28 ,  H01L21/00 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/74 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/78612 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/66772

Abstract: PROBLEM TO BE SOLVED: To provide the structure of a CMOS device and a method for manufacturing the CMOS device.
SOLUTION: The manufacturing method comprises a process of sticking an SOI wafer 20 having prescribed thickness to the surface of a buried oxide (BOX) substrate 10, a process of forming a gate dielectric 25 on the surface of the SOI wafer 20, a process of forming a shallow trench isolation (STI) area 35 so as to form an almost round corner on the BOX substrate 10, a process of forming gate structure on the surface of the gate dielectric 25, a process of sticking a driving layer to the surface of the SOI wafer 20, a process for executing either one of N-type dopant implanting and P-type dopant implanting in the SOI wafer 20 and the implanting layer, and a process of forming a source/drain region 79(a) from the implanting layer and the SOI wafer 20. The source/drain region 79(a) has thickness larger than the prescribed thickness of the SOI wafer 20, and the gate dielectric is arranged lower than the STI region 35.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2001298171A

公开(公告)日：2001-10-26

申请号：JP2001075111

申请日：2001-03-15

Applicant: IBM

Inventor： GAUTHIER JR ROBERT J ,  SCHEPIS DOMINIC J ,  STEPHEN H WOHLDMAN

IPC: H01L27/04 ,  H01L21/762 ,  H01L21/822 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit provided with an insulator for diffusing heat from a high output device while using high-K insulating materials and for dealing with the needs of a low dielectric constant and a low resistivity for a low output logic device while using low-K insulating materials at the same time. SOLUTION: The method and the structure for forming an integrated circuit wafer are provided with a step for forming a substrate 10 having first and second parts, a step for sticking a first insulator 11 on the substrate, a step for patterning the first insulator so that the first insulator can remain only on the first part, a step for sticking a second insulator 12 on the substrate (the first insulator has heat diffusing characteristics different from the second insulator, a step for forming a planar surface by polishing the second insulator, and a step for sticking a silicon film 13 on the first insulator and the second insulator.

公开(公告)号：JP2002261278A

公开(公告)日：2002-09-13

申请号：JP2002004187

申请日：2002-01-11

Applicant: IBM

Inventor： AJMERA ATUL C ,  FUNG KA HING ,  KU VICTOR ,  SCHEPIS DOMINIC J

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for reducing overlapping capaci tance between a gate and source/drain in a MOSFET element. SOLUTION: A notched gate MOS element includes an encapsulated low- permittivity material or capsuled air or vacuum on the bottom of the notched gate. Capacitance loss is reduced greatly on the part due to low permittivity on an interface between the gate and the source/drain.

公开(公告)号：JP2000243944A

公开(公告)日：2000-09-08

申请号：JP2000035433

申请日：2000-02-14

Applicant: IBM

Inventor： LEOBANDUNG EFFENDI ,  SADANA DEVENDRA K ,  SCHEPIS DOMINIC J ,  SHAHIDI GHAVAM

IPC: H01L21/205 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide a planar silicon-on-insulator(SOI) structure and a method for manufacturing the structure. SOLUTION: The SOI structure has a silicon wafer 10, an oxide layer 12 and a silicon layer 14. A trench is formed as extended from an upper surface of the structure to the silicon wafer, and the trench is filled with semiconductor 34. The trench has an upper part, a bottom surface and a sidewall. The sidewall has a sidewall silicon part. The sidewall silicon part of the trench sidewall is covered with a trench sidewall oxide layer 30. A protective sidewall 32 is formed on the trench sidewall and a trench sidewall oxide layer as extended from the upper part of the trench to the bottom surface of the trench.

公开(公告)号：WO2012012154A3

公开(公告)日：2012-04-26

申请号：PCT/US2011042289

申请日：2011-06-29

Applicant: IBM ,  KWON OH-JUNG ,  LEE JUNEDONG ,  PARRIES PAUL C ,  SCHEPIS DOMINIC J

Inventor： KWON OH-JUNG ,  LEE JUNEDONG ,  PARRIES PAUL C ,  SCHEPIS DOMINIC J

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L21/2007 ,  G06F17/5068 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/76251 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/40 ,  H01L28/90 ,  H01L29/66181

Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

Abstract translation: 提供了用于制造隔离电容器的结构和方法。 该方法包括通过SOI和掺杂多晶层同时形成围绕多个深沟槽的组或阵列的多个深沟槽和一个或多个隔离沟槽至下伏绝缘体层。 该方法还包括用绝缘体材料衬里多个深沟槽和一个或多个隔离沟槽。 该方法还包括在绝缘体材料上用导电材料填充多个深沟槽和一个或多个隔离沟槽。 深沟槽形成深沟槽电容器，并且一个或多个隔离沟槽形成将一个或多个深沟槽电容器的组或阵列与深沟槽电容器的另一组或阵列隔离的一个或多个隔离板。