Invention Patent
- Patent Title: COMPOUNDING PREPROCESSOR FOR CACHE
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Application No.: CA2040304Application Date: 1991-04-12
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Publication No.: CA2040304CPublication Date: 1995-04-11
- Inventor: BLANER BARTHOLOMEW , VASSILIADIS STAMATIS
- Applicant: IBM
- Assignee: IBM
- Current Assignee: IBM
- Priority: US52229190 1990-05-10
- Main IPC: G06F15/00
- IPC: G06F15/00 ; G06F9/00 ; G06F9/38 ; G06F12/08 ; G06F15/76
Abstract:
A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
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