公开(公告)号：EP0545927A4

公开(公告)日：1993-04-26

申请号：EP91908085

申请日：1991-03-29

Applicant: IBM

Inventor： VASSILIADIS STAMATIS ,  BLANER BARTHOLOMEW ,  JEREMIAH THOMAS LEO

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC classification number: G06F9/3853 ,  G06F9/30152 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3812 ,  G06F9/382 ,  G06F9/3885

Abstract: An instruction processor system for decoding compound instructions created from a series of base instruction (21) of a scalar machine, the processor generating a series of compound instruction (33) with an instruction format text having appened control bits in the instruction format text enabling the execution of the compound instruction format text in said instruction processor with a compounding facility (42) which fetches and decodes compound instructions which can be executed as compounded and single instructions by the arithmetic and logic units (26) of the instruction processor while preserving intact the scalar execution of the base instructions of a scalar machine which were originally in storage. The system nullifies any execution of a member instruction unit of a compound instruction upon occurrence of possible conditions, such as branch wich would affect the correctness of recording results of execution of the member instruction unit portion based upon the interrelationship of member units of the compound instruction with other instructions. The resultant series of compounded instructions generally executes in a faster manner than the original format which is preserved due to the parallel nature of the compounded instruction stream which is executed.

公开(公告)号：JPH0776924B2

公开(公告)日：1995-08-16

申请号：JP9609491

申请日：1991-04-03

Applicant: IBM

Inventor： BLANER BARTHOLOMEW ,  VASSILIADIS STAMATIS

IPC: G06F15/00 ,  G06F9/00 ,  G06F9/38 ,  G06F12/08 ,  G06F15/76

公开(公告)号：JPH0683623A

公开(公告)日：1994-03-25

申请号：JP9609791

申请日：1991-04-03

Applicant: IBM

Inventor： BLANER BARTHOLOMEW ,  VASSILIADIS STAMATIS

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/44 ,  G06F12/08

Abstract: PURPOSE: To provide a digital computer system in which computer instructions can be executed in parallel, and which includes a cache storage unit which temporarily stores the computer instruction in a machine level in a process from a higher level storage unit to a functional unit which processes the instruction in the computer system. CONSTITUTION: An instruction composite unit 37 arranged between a high level storage unit 36 and a cache storage unit 38 operates the analysis of an instruction, and generates composite information indicating whether or not this instruction can be processed in parallel to the adjacent instruction in an instruction stream to each instruction. Then, those instructions with a tag and the composite information are stored in the cache unit 38. Plural functional instruction processing units 39-41 which are operated in parallel are included in this computer system.

公开(公告)号：JPH0778737B2

公开(公告)日：1995-08-23

申请号：JP9609791

申请日：1991-04-03

Applicant: IBM

Inventor： BLANER BARTHOLOMEW ,  VASSILIADIS STAMATIS

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/44 ,  G06F12/08

公开(公告)号：JPH04230528A

公开(公告)日：1992-08-19

申请号：JP9609491

申请日：1991-04-03

Applicant: IBM

Inventor： BLANER BARTHOLOMEW ,  VASSILIADIS STAMATIS

IPC: G06F15/00 ,  G06F9/00 ,  G06F9/38 ,  G06F12/08 ,  G06F15/76

Abstract: PURPOSE: To provide a system where more than two computer instructions are processed in parallel. CONSTITUTION: A cache storage unit temporarily storing a machine level computer instruction is provided in the midst of function units 13-15 which processes the instruction from a host storage unit 10. An instruction composite conversion unit 11 which analyzes the instruction between the host storage unit and the cache storage unit and adds a tag field indicating whether or not the respective instructions are processed in parallel with more than one adjacent instruction of an instruction stream is provided. The instruction with a tag is stored in the cache unit. Moreover, Plural function instruction processing units which are mutually operated in parallel are provided. The instruction where the tag is given for a parallel processing is transmitted to the different one of the function units 13-15 in accordance with the code of an operation code fields.

公开(公告)号：DE69132271D1

公开(公告)日：2000-08-03

申请号：DE69132271

申请日：1991-03-29

Applicant: IBM

Inventor： VASSILIADIS STAMATIS ,  BLANER BARTHOLOMEW ,  JEREMIAH LEO

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38

公开(公告)号：CZ279899B6

公开(公告)日：1995-08-16

申请号：CS93391

申请日：1991-04-04

Applicant: IBM

Inventor： BLANER BARTHOLOMEW ,  VASSILIADIS STAMATIS

IPC: G06F15/00 ,  G06F9/00 ,  G06F9/38 ,  G06F12/08 ,  G06F15/76

公开(公告)号：DE68923262D1

公开(公告)日：1995-08-03

申请号：DE68923262

申请日：1989-11-24

Applicant: IBM

Inventor： VASSILIADIS STAMATIS ,  SCHWARZ ERIC MARK ,  SUNG BAIK MOON

IPC: G06F7/52 ,  G06F7/53 ,  G06F7/533

Abstract: A multi-bit overlapped scanning multiplication system using overlapped partial products in a matrix, accepts and multiplies either sign-magnitude operands or signed binary operands without correction, conversion, or complementation of operands or results.

公开(公告)号：PL289723A1

公开(公告)日：1992-05-04

申请号：PL28972391

申请日：1991-04-03

Applicant: IBM

Inventor： VASSILIADIS STAMATIS ,  EICKEMEYER RICHARD JAMES

IPC: G06F9/30 ,  G06F9/38 ,  G06F13/00

Abstract: This is a method of compounding two or more instructions from an instruction stream without knowing the starting point or length of each individual instruction. All instructions include one OP Code at a predetermined field location which identifies the instruction and its length. Those instructions which qualify need to have appropriate tags to indicate they are candidates for compounding. In System 370 where instructions are either 2,4 or 6 bytes in length, the field positions for the OP Code are presumed based on an estimated instruction length code. The value of each tag based on a presumed OP Code is recorded, and the instruction length code in the presumed OP Code is used to locate a complete sequence of possible instructions. Once an actual instruction boundary is found, the corresponding correct tag values are used to identify the commencement of a compound instruction, and other incorrectly generated tags are ignored.

公开(公告)号：HUT57456A

公开(公告)日：1991-11-28

申请号：HU110291

申请日：1991-04-04

Applicant: IBM

Inventor： VASSILIADIS STAMATIS ,  EICHEMEYER RICHARD JAMES

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/40

Abstract: This is a method of compounding two or more instructions from an instruction stream without knowing the starting point or length of each individual instruction. All instructions include one OP Code at a predetermined field location which identifies the instruction and its length. Those instructions which qualify need to have appropriate tags to indicate they are candidates for compounding. In System 370 where instructions are either 2,4 or 6 bytes in length, the field positions for the OP Code are presumed based on an estimated instruction length code. The value of each tag based on a presumed OP Code is recorded, and the instruction length code in the presumed OP Code is used to locate a complete sequence of possible instructions. Once an actual instruction boundary is found, the corresponding correct tag values are used to identify the commencement of a compound instruction, and other incorrectly generated tags are ignored.