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    SYSTEM FOR PREPARING INSTRUCTIONS FOR INSTRUCTION PARALLEL PROCESSOR AND SYSTEM WITH MECHANISM FOR BRANCHING IN THE MIDDLE OF A COMPOUND INSTRUCTION.
    1.
    发明公开
    SYSTEM FOR PREPARING INSTRUCTIONS FOR INSTRUCTION PARALLEL PROCESSOR AND SYSTEM WITH MECHANISM FOR BRANCHING IN THE MIDDLE OF A COMPOUND INSTRUCTION. 失效
    设备来的命令与指令的并行处理器来准备和设备与程序到复合命令分行的中间。

    公开(公告)号：EP0545927A4

    公开(公告)日：1993-04-26

    申请号：EP91908085

    申请日：1991-03-29

    Applicant: IBM

    Inventor： VASSILIADIS STAMATIS ,  BLANER BARTHOLOMEW ,  JEREMIAH THOMAS LEO

    IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38

    CPC classification number: G06F9/3853 ,  G06F9/30152 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3812 ,  G06F9/382 ,  G06F9/3885

    Abstract: An instruction processor system for decoding compound instructions created from a series of base instruction (21) of a scalar machine, the processor generating a series of compound instruction (33) with an instruction format text having appened control bits in the instruction format text enabling the execution of the compound instruction format text in said instruction processor with a compounding facility (42) which fetches and decodes compound instructions which can be executed as compounded and single instructions by the arithmetic and logic units (26) of the instruction processor while preserving intact the scalar execution of the base instructions of a scalar machine which were originally in storage. The system nullifies any execution of a member instruction unit of a compound instruction upon occurrence of possible conditions, such as branch wich would affect the correctness of recording results of execution of the member instruction unit portion based upon the interrelationship of member units of the compound instruction with other instructions. The resultant series of compounded instructions generally executes in a faster manner than the original format which is preserved due to the parallel nature of the compounded instruction stream which is executed.

    DIGITAL COMPUTER SYSTEM
    3.
    发明专利
    DIGITAL COMPUTER SYSTEM 失效

    公开(公告)号：JPH04230528A

    公开(公告)日：1992-08-19

    申请号：JP9609491

    申请日：1991-04-03

    Applicant: IBM

    Inventor： BLANER BARTHOLOMEW ,  VASSILIADIS STAMATIS

    IPC: G06F15/00 ,  G06F9/00 ,  G06F9/38 ,  G06F12/08 ,  G06F15/76

    Abstract: PURPOSE: To provide a system where more than two computer instructions are processed in parallel. CONSTITUTION: A cache storage unit temporarily storing a machine level computer instruction is provided in the midst of function units 13-15 which processes the instruction from a host storage unit 10. An instruction composite conversion unit 11 which analyzes the instruction between the host storage unit and the cache storage unit and adds a tag field indicating whether or not the respective instructions are processed in parallel with more than one adjacent instruction of an instruction stream is provided. The instruction with a tag is stored in the cache unit. Moreover, Plural function instruction processing units which are mutually operated in parallel are provided. The instruction where the tag is given for a parallel processing is transmitted to the different one of the function units 13-15 in accordance with the code of an operation code fields.

    COMPOUNDED PREPROCESSOR SYSTEM FOR CACHE
    4.
    发明专利
    COMPOUNDED PREPROCESSOR SYSTEM FOR CACHE 失效

    公开(公告)号：JPH0683623A

    公开(公告)日：1994-03-25

    申请号：JP9609791

    申请日：1991-04-03

    Applicant: IBM

    Inventor： BLANER BARTHOLOMEW ,  VASSILIADIS STAMATIS

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/44 ,  G06F12/08

    Abstract: PURPOSE: To provide a digital computer system in which computer instructions can be executed in parallel, and which includes a cache storage unit which temporarily stores the computer instruction in a machine level in a process from a higher level storage unit to a functional unit which processes the instruction in the computer system. CONSTITUTION: An instruction composite unit 37 arranged between a high level storage unit 36 and a cache storage unit 38 operates the analysis of an instruction, and generates composite information indicating whether or not this instruction can be processed in parallel to the adjacent instruction in an instruction stream to each instruction. Then, those instructions with a tag and the composite information are stored in the cache unit 38. Plural functional instruction processing units 39-41 which are operated in parallel are included in this computer system.

    APPARATUS AND METHOD FOR IMPLEMENTING SPECULATIVE CLOCK GATING OF DIGITAL LOGIC CIRCUITS
    6.
    发明申请
    APPARATUS AND METHOD FOR IMPLEMENTING SPECULATIVE CLOCK GATING OF DIGITAL LOGIC CIRCUITS 审中-公开
    实现数字逻辑电路的时钟调节的装置和方法

    公开(公告)号：WO2009094674A3

    公开(公告)日：2010-01-21

    申请号：PCT/US2009035251

    申请日：2009-02-26

    Applicant: IBM ,  BLANER BARTHOLOMEW ,  BROWN MARY D ,  BURKY WILLIAM E ,  VENTON TODD A

    Inventor： BLANER BARTHOLOMEW ,  BROWN MARY D ,  BURKY WILLIAM E ,  VENTON TODD A

    IPC: G06F1/00

    CPC classification number: G06F1/3203 ,  G06F1/10 ,  G06F1/3237 ,  Y02D10/128

    Abstract: A method for implementing speculative clock gating of digital logic circuits in a multiple stage pipeline design includes generating, in a first pipeline stage n, a valid control signal that is input to a first register (112) in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and generating, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers (116) in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs (202) used in generating the valid control signal, and wherein the clock signal is sent directly, without gating, to the first register (112) in the second pipeline stage.

    Abstract translation: 一种用于在多级流水线设计中实现数字逻辑电路的推测时钟门控的方法包括在第一流水线级n中产生输入到第二流水线级n + 1中的第一寄存器（112）的有效控制信号， 指示何时由第二流水线级n + 1执行操作的有效控制信号; 以及在所述第一流水线级中产生用于在第二流水线级中向多个附加寄存器（116）门控时钟信号的推测有效控制信号，其中所述推测有效控制信号仅使用 用于产生有效控制信号的控制输入（202）的总数，并且其中在第二流水线级中将时钟信号直接发送到第一流水线级的第一寄存器（112）。

    Erzeugen einer dynamischen Huffman-Tabelle
    7.
    发明专利
    Erzeugen einer dynamischen Huffman-Tabelle 未知

    公开(公告)号：DE102016220801B4

    公开(公告)日：2019-05-09

    申请号：DE102016220801

    申请日：2016-10-24

    Applicant: IBM

    Inventor： ABALI BULENT ,  BLANER BARTHOLOMEW ,  FRANKE HUBERTUS ,  REILLY JOHN J

    IPC: H03M7/40

    Abstract: Verfahren zum Codieren von Daten, wobei das Verfahren die Schritte aufweist:Realisieren von dynamischen Huffman-Tabellen in Hardware, die eine Mehrzahl von Huffman-Baumformen repräsentieren, welche aus einem Beispieldatensatz vorberechnet wurden, wobei die Huffman-Baumformen in den dynamischen Huffman-Tabellen durch Codelängenwerte repräsentiert werden;Entfernen von Symbolen aus den dynamischen Huffman-Tabellen, so dass lediglich variable Codelängenwerte verbleiben;Schreiben von Symbolen und ihren Zählwerten aus den Eingabedaten in die dynamischen Huffman-Tabellen nach dem Empfang von Eingabedaten;Berechnen einer Wertung für jede der dynamischen Huffman-Tabellen mit den Symbolen und Zählwerten aus den Eingabedaten, wobei die Wertung auf den Codelängenwerten der vorberechneten Huffman-Baumformen und den Zählwerten aus den Eingabedaten beruht; undAuswählen einer gegebenen der dynamischen Huffman-Tabellen mit einer niedrigsten Wertung für ein Codieren der Eingabedaten.

    Huffmann-Paralleldecoder
    8.
    发明专利
    Huffmann-Paralleldecoder 未知

    公开(公告)号：DE102016204602A1

    公开(公告)日：2016-09-29

    申请号：DE102016204602

    申请日：2016-03-21

    Applicant: IBM

    Inventor： ABALI BULENT ,  BLANER BARTHOLOMEW

    IPC: H03M7/40

    Abstract: Ein Halteregister weist einen Hauptdateneingang und einen Lookahead-Eingang auf. Aufeinanderfolgende sich überlappende Abschnitte des Hauptdateneingangs und des Lookahead-Eingangs werden für eine Mehrzahl M von Halbdecodern bereitgestellt, die eine Untergruppe von häufig vorkommenden Codewörtern eines Huffman-Codes enthalten. Wenn kein Codewort angetroffen wird, das nicht in den Halbdecodern verfügbar ist, entschlüsseln die Halbdecoder parallel in einem einzigen Taktzyklus M der häufig vorkommenden Codewörter. Wenn ein Codewort auftritt, das nicht in den Halbdecodern verfügbar ist, wird der Eingang, der für einen entsprechenden einen der Halbdecoder bestimmt ist, dessen Eingang das Codewort enthält, das nicht in dem entsprechenden einen der Halbdecoder verfügbar ist, auf einen Eingang eines Volldecoders angewendet, der in einem ternären inhaltsadressierbaren Arbeitsspeicher umgesetzt ist. Der Volldecoder enthält alle Codewörter des Huffman-Codes.

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