The invention relates to a failure analysis method of a memory chip. The failure analysis method comprises the following steps: determining a hot spot area where a failure point is located; confirmingword lines with electric leakage; applying bias voltage to the word lines with electric leakage, and the voltage contrast of the bit lines in the hot spot area is observed at the same time until failure bit lines with abnormal voltage contrast in the hot spot area are found; and performing failure analysis on the failure bit line. The method can improve the failure analysis efficiency.