Invention Patent
ITTO990356D0
未知
- Patent Title:
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Application No.: ITTO990356Application Date: 1999-04-30
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Publication No.: ITTO990356D0Publication Date: 1999-04-30
- Inventor: CORVASCE CHIARA , ZAMBRANO RAFFAELE
- Applicant: ST MICROELECTRONICS SRL
- Assignee: ST MICROELECTRONICS SRL
- Current Assignee: ST MICROELECTRONICS SRL
- Priority: ITTO990356 1999-04-30
- Main IPC: H01L21/8242
- IPC: H01L21/8242 ; H01L21/8246 ; H01L27/108 ; H01L27/115
Abstract:
The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material. In this way, the manufacturing process is not critical and the size of the cells is minimal.
Public/Granted literature
- IT1308465B1 Public/Granted day:2001-12-17
Information query
IPC分类: