公开(公告)号：JPH0342866A

公开(公告)日：1991-02-25

申请号：JP15412190

申请日：1990-06-14

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMBRANO RAFFAELE ,  MUSUMECI SALVATORE ,  RACITI SALVATORE

IPC: H01L21/8222 ,  H01L21/8248 ,  H01L27/06

Abstract: PURPOSE: To improve the dynamic characteristics of a power stage by using a bipolar mode field-effect transistor(BMFET), to maximize the current handling capacity and robustness of the power stage. CONSTITUTION: An n -type epitaxial layer 2 is grown on an n-type substrate 1 made of a high-impurity concn. single crystal Si, a p -type region is formed to constitute a lateral separation region of a component of an integrated control circuit, and n -type region 4 acting as a buried collector layer of a transistor of this control circuit. At this time a new epitaxial layer extending over the entire chip region is grown to form an n-type region 5. A p -type regions 6, 7 are formed with an n -type regions 10, 11, formed as a source of a BMFET and as a collector sink to reduce the series resistance of a low-voltage transistor. A base and emitter regions 12, 13 of an npn low-voltage transistor are formed, and contacts are formed to interconnect elements of a semiconductor device by metallizing and photomasking.

公开(公告)号：JP2000332224A

公开(公告)日：2000-11-30

申请号：JP2000130698

申请日：2000-04-28

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMBRANO RAFFAELE

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L27/08 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of an SOI type integrated circuit structure, which can manufacture an MOS element and a CMOS element at a low cost, and has structure and function capable of overcoming defects which the conventional SOI type integrated circuit structure has. SOLUTION: This manufacturing method of a plurality of SOI type circuit structures integrated on a semiconductor substrate 1, having a first conductivity- type contains a process forming at least a well 2 having a second conductivity- type on the semiconductor substrate 1, a process forming a hole 4 in at least the well 2, a process covering the hole 4 with an insulating layer 5, a process forming an aperture 6 in the bottom part of the hole 4 by penetrating the insulating layer 5, and a process filling the hole 4 with an epitaxial layer 7 grown from nuclei which can be reached through the aperture 6.

公开(公告)号：JP2000124410A

公开(公告)日：2000-04-28

申请号：JP28987399

申请日：1999-10-12

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMBRANO RAFFAELE

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108 ,  H01L27/115

Abstract: PROBLEM TO BE SOLVED: To provide a contact structure that has a structural, functional feature to overcome restrictions and/or problems attendant on a usual contact and is easily integrated into an integrated circuit, by a method wherein the contact structure is improved in integration properties to an integrated electronic device equipped with electronic elements formed through a MOS process or the like. SOLUTION: A contact structure is for a semiconductor device equipped with a MOS element 3 and a capacitor element 4 integrated on a semiconductor layer, where a contact 20 is provided inside openings 10 and 11 bored in an insulating layer 12 above a semiconductor layer respectively, and the surface edges, inner walls, and bases of the openings 10 and 11 are covered with a metal layer 18, and the openings 10 and 11 are filled up with insulating resin layer 19.

公开(公告)号：DE60140757D1

公开(公告)日：2010-01-21

申请号：DE60140757

申请日：2001-12-28

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMBRANO RAFFAELE ,  ARTONI CESARE

IPC: H01L27/115 ,  H01L21/02 ,  H01L21/8246 ,  H01L29/51

Abstract: A memory cell (30) of a stacked type is formed by a MOS transistor (32) and a ferroelectric capacitor (33). The MOS transistor (32) is formed in an active region (40) of a substrate (30) of semiconductor material and comprises a conductive region (34a). The ferroelectric capacitor (33) is formed on top of the active region and comprises a first and a second electrodes (45, 47) separated by a ferroelectric region (46). A contact region (44a) connects the conductive region (34a) of the MOS transistor to the first electrode (45) of the ferroelectric capacitor (33). The ferroelectric capacitor (33) has a non-planar structure, formed by a horizontal portion (45) and two side portions (48) extending transversely to, and in direct electrical contact with, the horizontal portion.

公开(公告)号：DE69739202D1

公开(公告)日：2009-02-26

申请号：DE69739202

申请日：1997-11-14

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMBRANO RAFFAELE

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/285

公开(公告)号：IT1320408B1

公开(公告)日：2003-11-26

申请号：ITTO20000543

申请日：2000-06-06

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMBRANO RAFFAELE

IPC: G11C17/12

Abstract: The ROM memory cell, not decodable by visual inspection comprises a substrate of semiconductor material having a first conductivity type, in particular P-. A first MOS device having a first threshold voltage is formed in a first portion of the substrate, and a MOS device having a second threshold voltage, greater than the first threshold voltage, is formed in a second portion of the substrate adjacent to the first portion. The second MOS device is a diode reverse biased during a reading phase of the ROM memory cell and comprises a source region having the first conductivity type and a drain region having a second conductivity type. The source region has a level of doping higher than that of the substrate.

公开(公告)号：IT1308465B1

公开(公告)日：2001-12-17

申请号：ITTO990356

申请日：1999-04-30

Applicant: ST MICROELECTRONICS SRL

Inventor： CORVASCE CHIARA ,  ZAMBRANO RAFFAELE

IPC: H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/115

Abstract: The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material. In this way, the manufacturing process is not critical and the size of the cells is minimal.

公开(公告)号：IT1312269B1

公开(公告)日：2002-04-10

申请号：ITMI990919

申请日：1999-04-30

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMBRANO RAFFAELE ,  CORVASCE CHIARA

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/115

Abstract: Presented is a ferroelectric non-volatile memory cell in a semiconductor substrate that has a MOS device connected in parallel to a ferroelectric capacitor. The MOS device has first and second conduction terminals and is covered with an insulating layer. The ferroelectric capacitor has a lower electrode formed on the insulating layer above the first conduction terminals and are electrically coupled to them. The lower electrode of the ferroelectric capacitor is covered with a layer of ferroelectric material and coupled capacitively to an upper electrode. The upper electrode is formed above the second conduction terminals and are electrically connected thereto, and extends over the ferroelectric material to at least partially overlap the lower electrode. Also presented is a non-volatile memory matrix that includes a plurality of the ferroelectric memory cells that are organized into rows and columns.

公开(公告)号：DE69426565D1

公开(公告)日：2001-02-15

申请号：DE69426565

申请日：1994-09-21

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： PALARA SERGIO ,  ZAMBRANO RAFFAELE

IPC: H01L27/04 ,  H01L27/02 ,  H01L29/78 ,  H03K17/08 ,  H03K17/687

公开(公告)号：ITTO990356A1

公开(公告)日：2000-10-30

申请号：ITTO990356

申请日：1999-04-30

Applicant: ST MICROELECTRONICS SRL

Inventor： CORVASCE CHIARA ,  ZAMBRANO RAFFAELE

IPC: H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/115

Abstract: The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material. In this way, the manufacturing process is not critical and the size of the cells is minimal.