Invention Patent
- Patent Title: METHOD AND CIRCUIT FOR PREVENTING GENERATION OF LATCH-DOWN PHENOMENON OF TRANSISTOR,AND TRANSISTOR AND VOLTAGE REGULATOR OF USING THE METHOD AND CIRCUIT
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Application No.: JP27290595Application Date: 1995-10-20
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Publication No.: JPH08288810APublication Date: 1996-11-01
- Inventor: JIYOBUANNI GATSURI , JIYUZETSUPE SHITSURA
- Applicant: CONS RIC MICROELETTRONICA
- Assignee: CONS RIC MICROELETTRONICA
- Current Assignee: CONS RIC MICROELETTRONICA
- Priority: EP94830502 1994-10-27
- Main IPC: H01L27/04
- IPC: H01L27/04 ; H01L21/822 ; H01L27/06 ; H03F1/52 ; H03K17/08
Abstract:
PROBLEM TO BE SOLVED: To provide a method and a circuit for preventing a latch-down phenomenon at a transistor protected from the runaway of its safe operating area(SOA). SOLUTION: By adding a 1st protection circuit PCI(for the runaway of SOA) having a 2nd protection circuit PC2 for driving the control terminal of transistor PT so as not to be affected by a load watched from the output terminal of transistor PT while keeping the value of current flowing through a main conduction path almost constant when that value tends to drop lower than a prescribed downside limit value because of 1st protection in the case of increasing a voltage loaded to the main conduction path of transistor PT, the transistor PT can always supply a correspondent current to the load up to an upside breakdown limit value, VMAX allowable for this transistor PT.
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