Invention Grant
- Patent Title: Error processing method, memory storage device and memory controlling circuit unit
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Application No.: US14565437Application Date: 2014-12-10
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Publication No.: US10067824B2Publication Date: 2018-09-04
- Inventor: Wei Lin , Yu-Cheng Hsu , Shao-Wei Yen , Tien-Ching Wang , Yu-Hsiang Lin , Kuo-Hsin Lai , Li-Chun Liang
- Applicant: PHISON ELECTRONICS CORP.
- Applicant Address: TW Miaoli
- Assignee: PHISON ELECTRONICS CORP.
- Current Assignee: PHISON ELECTRONICS CORP.
- Current Assignee Address: TW Miaoli
- Agency: JCIPRNET
- Priority: TW103134558A 20141003
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/10 ; G11C29/52 ; G11C29/42 ; G11C29/44 ; G11C11/56 ; G11C16/34 ; G11C29/04

Abstract:
An error processing method for a rewritable non-volatile memory module, a memory storage device and a memory controlling circuit unit are provided. The rewritable non-volatile memory module includes a plurality of memory cells. The error processing method includes: sending a first read command sequence for reading a plurality of bits from the memory cells; performing a first decoding on the bits; determining whether each error belongs to a first type error or a second type error if the bits have at least one error; recording related information of a first error in the at least one error if the first error belongs to the first type error; and not recording the related information of the first error if the first error belongs to the second type error. Accordingly, errors with particular type may be processed suitably.
Public/Granted literature
- US20160098316A1 ERROR PROCESSING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT Public/Granted day:2016-04-07
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