Invention Grant
- Patent Title: Facilitating dynamic pipelining of workload executions on graphics processing units on computing devices
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Application No.: US14574606Application Date: 2014-12-18
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Publication No.: US10068306B2Publication Date: 2018-09-04
- Inventor: Jayanth N. Rao , Pavan K. Lanka
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Womble Bond Dickinson (US) LLP
- Main IPC: G06F9/50
- IPC: G06F9/50 ; G06T1/20 ; G06F9/46 ; H03K99/00

Abstract:
A mechanism is described for facilitating dynamic pipelining of workload executions at graphics processing units on computing devices. A method of embodiments, as described herein, includes generating a command buffer having a plurality of kernels relating to a plurality of workloads to be executed at a graphics processing unit (GPU), and pipelining the workloads to be processed at the GPU, where pipelining includes scheduling each kernel to be executed on the GPU based on at least one of availability of resource threads and status of one or more dependency events relating to each kernel in relation to other kernels of the plurality of kernels.
Public/Granted literature
- US20160180486A1 FACILITATING DYNAMIC PIPELINING OF WORKLOAD EXECUTIONS ON GRAPHICS PROCESSING UNITS ON COMPUTING DEVICES Public/Granted day:2016-06-23
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