公开(公告)号：US20170300361A1

公开(公告)日：2017-10-19

申请号：US15201496

申请日：2016-07-03

Applicant: INTEL CORPORATION

Inventor： Pavan K. Lanka ,  Krzysztof Laskowski ,  Michal Mrozek

IPC: G06F9/50 ,  G06F9/48

CPC classification number: G06F9/4881 ,  Y02D10/24

Abstract: Methods and apparatus relating to employing out-of-order queues for improved GPU (Graphics Processing Unit) utilization are described. In an embodiment, logic is used to employ out-of-order queues for improved GPU (Graphics Processing Unit) utilization. Other embodiments are also disclosed and claimed.

公开(公告)号：US10068306B2

公开(公告)日：2018-09-04

申请号：US14574606

申请日：2014-12-18

Applicant: INTEL CORPORATION

Inventor： Jayanth N. Rao ,  Pavan K. Lanka

IPC: G06F9/50 ,  G06T1/20 ,  G06F9/46 ,  H03K99/00

Abstract: A mechanism is described for facilitating dynamic pipelining of workload executions at graphics processing units on computing devices. A method of embodiments, as described herein, includes generating a command buffer having a plurality of kernels relating to a plurality of workloads to be executed at a graphics processing unit (GPU), and pipelining the workloads to be processed at the GPU, where pipelining includes scheduling each kernel to be executed on the GPU based on at least one of availability of resource threads and status of one or more dependency events relating to each kernel in relation to other kernels of the plurality of kernels.

公开(公告)号：US10521874B2

公开(公告)日：2019-12-31

申请号：US14498220

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Jayanth N. Rao ,  Pavan K. Lanka ,  Michal Mrozek

IPC: G06T1/20 ,  G06T1/60

Abstract: An apparatus and method are described for executing workloads without host intervention. For example, one embodiment of an apparatus comprises: a host processor; and a graphics processor unit (GPU) to execute a hierarchical workload responsive to one or more commands issued by the host processor, the hierarchical workload comprising a parent workload and a plurality of child workloads interconnected in a logical graph structure; and a scheduler kernel implemented by the GPU to schedule execution of the plurality of child workloads without host intervention, the scheduler kernel to evaluate conditions required for execution of the child workloads and determine an order in which to execute the child workloads on the GPU based on the evaluated conditions; the GPU to execute the child workloads in the order determined by the scheduler kernel and to provide results of parent and child workloads to the host processor following execution of all of the child workloads.