Invention Grant
- Patent Title: Group III-N transistor on nanoscale template structures
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Application No.: US15656480Application Date: 2017-07-21
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Publication No.: US10096683B2Publication Date: 2018-10-09
- Inventor: Han Wui Then , Sansaptak Dasgupta , Marko Radosavljevic , Benjamin Chu-Kung , Sanaz Gardner , Seung Hoon Sung , Robert S. Chau
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/66 ; H01L29/20 ; H01L29/80 ; H01L29/78 ; H01L21/02 ; H01L21/285 ; H01L21/84 ; H01L29/06 ; H01L29/201 ; H01L29/778 ; H01L21/283 ; H01L29/423

Abstract:
A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.
Public/Granted literature
- US20170323946A1 GROUP III-N TRANSISTOR ON NANOSCALE TEMPLATE STRUCTURES Public/Granted day:2017-11-09
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