Invention Grant
- Patent Title: On-chip power sequence validator and monitor
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Application No.: US15275034Application Date: 2016-09-23
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Publication No.: US10254811B2Publication Date: 2019-04-09
- Inventor: Donald L. Cheung , Anup Chakravarthi Suggula
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Meyertons Hood Kivlin Kowert and Goetzel PC
- Agent Rory D. Rankin
- Main IPC: G06F1/26
- IPC: G06F1/26 ; G06F1/28 ; G06F1/32 ; G06F11/07 ; G06F1/3206 ; G06F1/3296

Abstract:
Systems, apparatuses, and methods for monitoring power rails during power sequences are disclosed. An apparatus includes one or more voltage regulators, a plurality of registers, and control logic. The control logic is configured to monitor a power rail generated by a voltage regulator. The control logic generates and stores an indication of pass or failure in a first register for the power rail during a power sequence. The control logic enables the first register to be read by an external device subsequent to completion of the power sequence. In another embodiment, the control logic generates a pass indicator if the power rail is less than a first voltage value on a first boundary of a timing interval and if the power rail is greater than a second voltage value on a second boundary of the timing interval. Otherwise, a fail indicator is generated.
Public/Granted literature
- US20180088649A1 ON-CHIP POWER SEQUENCE VALIDATOR AND MONITOR Public/Granted day:2018-03-29
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