Invention Grant
- Patent Title: Disconnect cavity by plating resist process and structure
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Application No.: US15159665Application Date: 2016-05-19
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Publication No.: US10292279B2Publication Date: 2019-05-14
- Inventor: Jiawen Chen , Pui Yin Yu
- Applicant: Multek Technologies Limited
- Applicant Address: US CA San Jose
- Assignee: Multek Technologies Limited
- Current Assignee: Multek Technologies Limited
- Current Assignee Address: US CA San Jose
- Agency: Haverstock & Owens LLP
- Priority: CN201610268670 20160427
- Main IPC: H05K3/42
- IPC: H05K3/42 ; H05K3/10 ; H05K1/11 ; H05K3/46 ; H05K1/02

Abstract:
A disconnect cavity is formed within a PCB, where the disconnect cavity is electrically disconnected from a PCB landing layer. The disconnect cavity is formed using a plating resist process which does not require low flow prepreg nor selective copper etching. Plating resist is printed on a core structure selectively positioned within a PCB stack-up. The volume occupied by the plating resist forms a subsequently formed disconnect cavity. After lamination of the PCB stack-up, depth control milling, drilling and electroless copper plating are performed, followed by a plating resist stripping process to substantially remove the plating resist and all electroless copper plated to the plating resist, thereby forming the disconnect cavity. In a subsequent copper plating process, without electric connectivity copper cannot be plated to the side walls and bottom surface of the disconnect cavity, resulting in the disconnect cavity wall being electrically disconnected from the PCB landing layer.
Public/Granted literature
- US20170318685A1 DISCONNECT CAVITY BY PLATING RESIST PROCESS AND STRUCTURE Public/Granted day:2017-11-02
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