Invention Grant
- Patent Title: Performance-aware and reliability-aware data placement for n-level heterogeneous memory systems
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Application No.: US15331270Application Date: 2016-10-21
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Publication No.: US10365996B2Publication Date: 2019-07-30
- Inventor: Manish Gupta , David A. Roberts , Mitesh R. Meswani , Vilas Sridharan , Steven Raasch , Daniel I. Lowell
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Volpe and Koenig, P.C.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/02

Abstract:
Techniques for selecting one of a plurality of heterogeneous memory units for placement of blocks of data (e.g., memory pages), based on both reliability and performance, are disclosed. A “cost” for each data block/memory unit combination is determined, based on the frequency of access of the data block, the latency of the memory unit, and, optionally, an architectural vulnerability factor (which represents the level of exposure of a particular memory data value to memory faults such as bit flips). A memory unit is selected for the data block for which the determined cost is the lowest, out of all memory units considered, and the data block is placed into that memory unit.
Public/Granted literature
- US20170277441A1 PERFORMANCE-AWARE AND RELIABILITY-AWARE DATA PLACEMENT FOR N-LEVEL HETEROGENEOUS MEMORY SYSTEMS Public/Granted day:2017-09-28
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