Invention Grant
- Patent Title: Method of applying vertex based corrections to a semiconductor design
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Application No.: US15534921Application Date: 2015-12-22
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Publication No.: US10534255B2Publication Date: 2020-01-14
- Inventor: Thomas Quaglio , Mathieu Millequant , Charles Tiphine
- Applicant: ASELTA NANOGRAPHICS
- Applicant Address: FR Grenoble
- Assignee: ASELTA NANOGRAPHICS
- Current Assignee: ASELTA NANOGRAPHICS
- Current Assignee Address: FR Grenoble
- Agency: Baker & Hostetler LLP
- Priority: EP14307169 20141223
- International Application: PCT/EP2015/081059 WO 20151222
- International Announcement: WO2016/102607 WO 20160630
- Main IPC: G03F1/78
- IPC: G03F1/78 ; G03F1/36 ; G03F1/20 ; G03F7/20 ; G06F17/50

Abstract:
A method of geometry corrections to properly transfer semiconductor designs on a wafer or a mask in nanometer scale processes is provided. In contrast with some prior art techniques, geometry corrections and possibly dose corrections are applied before fracturing. Unlike edge based corrections, where the edges are displaced in parallel, the displacements applied to generated geometry corrections do not preserve parallelism of the edges, which is specifically well suited for free form designs. A seed design is generated from the target design. Vertices connecting segments are placed along the seed design contour. Correction sites are placed on the segments. Displacement vectors are applied to the vertices. A simulated contour is generated and compared to the contour of the target design. The process is iterated until a match criteria between simulated and target design (or another stop criteria) is reached.
Public/Granted literature
- US20180267399A1 METHOD OF APPLYING VERTEX BASED CORRECTIONS TO A SEMICONDUCTOR DESIGN Public/Granted day:2018-09-20
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