An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to operate with the memory devices having a first data width in a first mode and with the memory devices having a second data width in a second mode. The control circuit may be configured to implement two differential data strobe input/output circuits. The differential data strobe input/output circuits each may have driver and termination control inputs that are independently programmable. The differential data strobe input/output circuits may be configured to be connected in parallel when the control circuit is operating in the second mode.