Invention Grant
- Patent Title: Embedded circuit patterning feature selective electroless
-
Application No.: US15588500Application Date: 2017-05-05
-
Publication No.: US10586715B2Publication Date: 2020-03-10
- Inventor: Yonggang Yong Li , Aritra Dhar , Dilan Seneviratne , Jon M. Williams
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L21/288
- IPC: H01L21/288 ; H01L21/48 ; H01L23/498 ; C23C18/16 ; C23C18/38 ; C23C18/20 ; C23C18/30 ; H05K3/10 ; H05K3/18 ; H05K3/00 ; H05K3/04 ; H01L23/00

Abstract:
Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.
Public/Granted literature
- US20170243762A1 EMBEDED CIRCUIT PATTERNING FEATURE SELECTIVE ELECTROLESS COPPER PLATING Public/Granted day:2017-08-24
Information query
IPC分类: