公开(公告)号：US10586715B2

公开(公告)日：2020-03-10

申请号：US15588500

申请日：2017-05-05

Applicant: Intel Corporation

Inventor： Yonggang Yong Li ,  Aritra Dhar ,  Dilan Seneviratne ,  Jon M. Williams

IPC: H01L21/288 ,  H01L21/48 ,  H01L23/498 ,  C23C18/16 ,  C23C18/38 ,  C23C18/20 ,  C23C18/30 ,  H05K3/10 ,  H05K3/18 ,  H05K3/00 ,  H05K3/04 ,  H01L23/00

Abstract: Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.

公开(公告)号：US20250112162A1

公开(公告)日：2025-04-03

申请号：US18375469

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Zheng Kang ,  Tchefor Ndukum ,  Yosuke Kanaoka ,  Jeremy Ecton ,  Gang Duan ,  Jefferson Kaplan ,  Yonggang Yong Li ,  Minglu Liu ,  Brandon C. Marin ,  Bai Nie ,  Srinivas Pietambaram ,  Shriya Seshadri ,  Bohan Shan ,  Deniz Turan ,  Vishal Bhimrao Zade

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

Abstract: An electronic package comprises a substrate core; one or more dielectric material layers over the substrate core and having a lower dielectric material layer, and a plurality of metallization layers comprising an upper-most metallization layer; an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer; and at least one conductive feature below and coupled to the IC die. A downwardly facing surface of the conductive feature is located on the lower dielectric material layer and defines a horizontal plane at a junction between the conductive feature and the lower dielectric material layer. The lower dielectric material layer has an upper facing surface facing in a direction of the IC die adjacent the conductive feature that is vertically offset from the horizontal plane.

公开(公告)号：US09646854B2

公开(公告)日：2017-05-09

申请号：US14229777

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Yonggang Yong Li ,  Aritra Dhar ,  Dilan Seneviratne ,  Jon M. Williams

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/48 ,  H05K3/10 ,  H05K3/18 ,  C23C18/16 ,  C23C18/20 ,  C23C18/30 ,  H01L23/498 ,  H05K3/00 ,  H05K3/04 ,  C23C18/38

CPC classification number: H01L21/4857 ,  C23C18/1608 ,  C23C18/1612 ,  C23C18/2086 ,  C23C18/30 ,  C23C18/38 ,  H01L21/288 ,  H01L21/486 ,  H01L21/4864 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/0032 ,  H05K3/045 ,  H05K3/107 ,  H05K3/185 ,  H05K2201/0236 ,  H05K2203/072 ,  H05K2203/107

Abstract: Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.