Invention Grant
- Patent Title: Cache memory with scrubber logic
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Application No.: US15920145Application Date: 2018-03-13
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Publication No.: US10678706B2Publication Date: 2020-06-09
- Inventor: Zvika Greenfield , Eshel Serlin , Asaf Rubinstein , Eli Abadi
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00 ; G06F13/28 ; G06F12/123 ; G06F12/126 ; G06F11/10 ; G06F12/121

Abstract:
Embodiments of the present disclosure are directed towards a computing device having a cache memory device with a scrubber logic. In some embodiments, the scrubber logic controller may be coupled with the cache device, and may perform a selection for eviction from the cache device a portion of data stored in the cache device, based at least in part on one or more selection criteria, at a dynamically adjusted level of aggressiveness of the selection performance. The scrubber logic controller may adjust the level of aggressiveness of the selection performance, based at least in part on a determined time left to complete the selection performance at a current level of aggressiveness. Other embodiments may be described and/or claimed.
Public/Granted literature
- US20190050346A1 CACHE MEMORY WITH SCRUBBER LOGIC Public/Granted day:2019-02-14
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