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    Memory controller for multi-level system memory with coherency unit
    1.
    发明授权
    Memory controller for multi-level system memory with coherency unit 有权

    公开(公告)号：US10204047B2

    公开(公告)日：2019-02-12

    申请号：US14671892

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Israel Diamand ,  Nir Misgav ,  Aravindh Anantaraman ,  Zvika Greenfield

    IPC: G06F12/0811

    Abstract: An apparatus is described that includes a memory controller having an interface to couple to a multi-level system memory. The memory controller also includes a coherency buffer and coherency services logic circuitry. The coherency buffer is to keep cache lines for which read and/or write requests have been received. The coherency services logic circuitry is coupled to the interface and the coherency buffer. The coherency services logic circuitry is to merge a cache line that has been evicted from a level of the multi-level system memory with another version of the cache line within the coherency buffer before writing the cache line back to a deeper level of the multi-level system memory if at least one of the following is true: the another version of said cache line is in a modified state; the memory controller has a pending write request for the cache line.

    Throttling support for row-hammer counters
    4.
    发明授权
    Throttling support for row-hammer counters 有权
    节流支持行锤计数器

    公开(公告)号：US09251885B2

    公开(公告)日：2016-02-02

    申请号：US13730181

    申请日：2012-12-28

    Applicant: Intel Corporation

    Inventor： Zvika Greenfield ,  Tomer Levy

    IPC: G11C11/406 ,  G06F13/16

    CPC classification number: G11C11/40607 ,  G06F13/1605 ,  G11C11/40603 ,  G11C11/40611

    Abstract: Throttling of memory access commands. Accesses to rows of a memory device are monitored for a timeframe. The timeframe is divided into at least two sub-frames. If the number of accesses for any of the rows during a first sub-frame exceeds a first threshold throttling accesses to the accessed row at a first rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the first threshold. The first threshold is associated with risk of data corruption on a row physically adjacent to the accessed row. If a number of accesses for the accessed row during a second sub-frame exceeds a second threshold, throttling accesses to the accessed row at a second rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the second threshold. The second threshold is greater than the first threshold. The second throttling rate is greater than the first throttling rate.

    Abstract translation: 调节内存访问命令。 在一段时间内监视访问存储设备的行。 时间框架被划分为至少两个子帧。 如果在第一子帧期间的任何行的访问次数超过第一阈值，则以第一速率限制对所访问的行的访问。 如果访问行的访问次数不超过第一个阈值，则不访问被访问的行。 第一个阈值与物理上与访问行相邻的行的数据损坏风险相关。 如果在第二子帧期间对所访问的行的访问次数超过第二阈值，则以第二速率限制对所访问的行的访问。 如果访问行的访问次数不超过第二个阈值，则不访问被访问的行。 第二阈值大于第一阈值。 第二节流率大于第一节流速率。

    Cache memory with scrubber logic
    5.
    发明授权
    Cache memory with scrubber logic 有权

    公开(公告)号：US10678706B2

    公开(公告)日：2020-06-09

    申请号：US15920145

    申请日：2018-03-13

    Applicant: INTEL CORPORATION

    Inventor： Zvika Greenfield ,  Eshel Serlin ,  Asaf Rubinstein ,  Eli Abadi

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/123 ,  G06F12/126 ,  G06F11/10 ,  G06F12/121

    Abstract: Embodiments of the present disclosure are directed towards a computing device having a cache memory device with a scrubber logic. In some embodiments, the scrubber logic controller may be coupled with the cache device, and may perform a selection for eviction from the cache device a portion of data stored in the cache device, based at least in part on one or more selection criteria, at a dynamically adjusted level of aggressiveness of the selection performance. The scrubber logic controller may adjust the level of aggressiveness of the selection performance, based at least in part on a determined time left to complete the selection performance at a current level of aggressiveness. Other embodiments may be described and/or claimed.

    Concurrent accesses of asymmetrical memory sources
    6.
    发明授权
    Concurrent accesses of asymmetrical memory sources 有权

    公开(公告)号：US10558570B2

    公开(公告)日：2020-02-11

    申请号：US15442470

    申请日：2017-02-24

    Applicant: Intel Corporation

    Inventor： Nadav Bonen ,  Zvika Greenfield ,  Randy Osborne

    IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/0871 ,  G06F13/16

    Abstract: Described herein are embodiments of asymmetric memory management to enable high bandwidth accesses. In embodiments, a high bandwidth cache or high bandwidth region can be synthesized using the bandwidth capabilities of more than one memory source. In one embodiment, memory management circuitry includes input/output (I/O) circuitry coupled with a first memory and a second memory. The I/O circuitry is to receive memory access requests. The memory management circuitry also includes logic to determine if the memory access requests are for data in a first region of system memory or a second region of system memory, and in response to a determination that one of the memory access requests is to the first region and a second of the memory access requests is to the second region, access data in the first region from the cache of the first memory and concurrently access data in the second region from the second memory.

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