Invention Grant
- Patent Title: Hierarchical wafer inspection
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Application No.: US16162539Application Date: 2018-10-17
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Publication No.: US10732128B2Publication Date: 2020-08-04
- Inventor: Menachem Regensburger
- Applicant: CAMTEK LTD.
- Agency: Reches Patent
- Main IPC: G01N21/95
- IPC: G01N21/95 ; G01N21/88 ; H01L21/66

Abstract:
There may be provided a method for evaluating an object, that may include evaluating a region of the object by a first evaluation module to provide first evaluation results that are related to multiple sites of the region; finding, using a mapping between values of first evaluation results and values of second evaluation results, (a) a first site of the multiple sites that does not require an evaluation by a second evaluation module, and (b) a second site of the multiple sites that requires an evaluation by the second evaluation module; wherein the second evaluation module is more reliable than the first evaluation module; evaluating the second site by the second evaluation module to provide second evaluation results of the second sites; estimating, based on first evaluation results of the first site and on the mapping, a state of the first site; and providing an evaluation of the region based on the state of the first site, and on the second evaluation result of the second site.
Public/Granted literature
- US20190128822A1 HIERARCHICAL WAFER INSPECTION Public/Granted day:2019-05-02
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