Invention Grant
- Patent Title: Methods of minimizing wafer backside damage in semiconductor wafer processing
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Application No.: US16437048Application Date: 2019-06-11
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Publication No.: US10971390B2Publication Date: 2021-04-06
- Inventor: Abdul Aziz Khaja , Liangfa Hu , Sudha S. Rathi , Ganesh Balasubramanian
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L21/687
- IPC: H01L21/687 ; H01L21/67

Abstract:
The present disclosure generally relates to substrate supports for semiconductor processing. In one embodiment, a substrate support is provided. The substrate support includes a body comprising a substrate chucking surface, an electrode disposed within the body, a plurality of substrate supporting features formed on the substrate chucking surface, wherein the number of substrate supporting features increases radially from a center of the substrate chucking surface to an edge of the substrate chucking surface, and a seasoning layer formed on the plurality of the substrate supporting features, the seasoning layer comprising a silicon nitride.
Public/Granted literature
- US20190393072A1 METHODS OF MINIMIZING WAFER BACKSIDE DAMAGE IN SEMICONDUCTOR WAFER PROCESSING Public/Granted day:2019-12-26
Information query
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