Invention Grant
- Patent Title: Semiconductor package with chamfered pads
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Application No.: US15815351Application Date: 2017-11-16
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Publication No.: US11056435B2Publication Date: 2021-07-06
- Inventor: Cheng-Lin Ho , Chung Chieh Chang , Ya Fang Chan , Chih-Cheng Lee
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Main IPC: H01L23/535
- IPC: H01L23/535 ; H01L21/02 ; H01L23/498 ; H01L23/00

Abstract:
At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device package. The substrate comprises a dielectric layer, a first conductive element adjacent to the dielectric layer, a second conductive element adjacent to the dielectric layer, and a third conductive element adjacent to the dielectric layer. The first conductive element has a first central axis in a first direction and a second central axis in a second direction. The first conductive element comprises a first chamfer and a second chamfer adjacent to the first chamfer. The second conductive element has a first central axis in the first direction and a second central axis in the second direction. The third conductive element has a first central axis in the first direction and a second central axis in the second direction. The first central axes of the first, second, and third conductive elements are substantially parallel to one another in the first direction and are misaligned from one another. The second central axes of the first and second conductive elements are substantially co-linear in the second direction. The second central axis of the third conductive element is substantially parallel to and misaligned from the second central axes of the first and second conductive elements. The first chamfer and the second chamfer are separated by at least one of the first central axis and the second central axis of the first conductive element and are substantially asymmetric.
Public/Granted literature
- US20190148297A1 SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME Public/Granted day:2019-05-16
Information query
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