Invention Grant
- Patent Title: Bottom fin trim isolation aligned with top gate for stacked device architectures
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Application No.: US16650155Application Date: 2018-01-10
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Publication No.: US11075202B2Publication Date: 2021-07-27
- Inventor: Aaron D. Lilak , Gilbert Dewey , Willy Rachmady , Patrick Morrow , Rishabh Mehandru
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- International Application: PCT/US2018/013138 WO 20180110
- International Announcement: WO2019/139572 WO 20190718
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/06 ; H01L29/417 ; H01L29/78

Abstract:
An integrated circuit structure includes a first portion of a bottom semiconductor fin extending horizontally in a length direction and vertically in a height direction, a second portion of the bottom semiconductor fin extending horizontally in the length direction and vertically in the height direction, a top semiconductor fin extending horizontally in the length direction and vertically in the height direction, and an insulator region extending horizontally in the length direction to electrically insulate the first portion of the bottom semiconductor fin from the second portion of the bottom semiconductor fin. The insulator region further extends vertically in the height direction in vertical alignment with the top semiconductor fin. The insulator region includes at least one of an insulator material and an airgap. In an embodiment, the top semiconductor fin is associated with a transistor, and the insulator region is in vertical alignment with a gate electrode of the transistor.
Public/Granted literature
- US20210074704A1 BOTTOM FIN TRIM ISOLATION ALIGNED WITH TOP GATE FOR STACKED DEVICE ARCHITECTURES Public/Granted day:2021-03-11
Information query
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