公开(公告)号：US12080605B2

公开(公告)日：2024-09-03

申请号：US17866122

申请日：2022-07-15

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan ,  Richard E. Schenker ,  Stephanie A. Bojarski ,  Willy Rachmady ,  Patrick R. Morrow ,  Jeffrey D. Bielefeld ,  Gilbert Dewey ,  Hui Jae Yoo

IPC: H01L21/8234 ,  H01L23/48 ,  H01L23/532 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/823475 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L23/481 ,  H01L23/53295 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/785

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

公开(公告)号：US11640961B2

公开(公告)日：2023-05-02

申请号：US16954126

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Aaron D. Lilak ,  Willy Rachmady ,  Rishabh Mehandru ,  Kimin Jun ,  Anh Phan ,  Hui Jae Yoo ,  Patrick Morrow ,  Cheng-Ying Huang ,  Matthew V. Metz

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.

公开(公告)号：US20230081882A1

公开(公告)日：2023-03-16

申请号：US17474689

申请日：2021-09-14

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Abhishek A. Sharma ,  Aaron D. Lilak ,  Hui Jae Yoo ,  Scott B. Clendenning ,  Van H. Le ,  Tristan A. Tronic ,  Urusa Alaan

IPC: H01L27/108 ,  H01L27/06 ,  G11C5/10

Abstract: A memory structure includes a spacer between a first side of a wordline conductor and a bitline conductor. A semiconductor material has horizontal portions extending from the bitline conductor along a top and bottom of the wordline conductor and has a contact portion extending along a second side of the wordline conductor between and connecting the horizontal portions. A high-κ dielectric is between the semiconductor material and the wordline conductor. A capacitor has a first conductor, a second conductor, and an insulator between the first and second conductors, where the first conductor contacts the contact portion of the semiconductor material along the first side of the wordline conductor, and the second conductor connects to a ground terminal.

公开(公告)号：US20220352029A1

公开(公告)日：2022-11-03

申请号：US17863292

申请日：2022-07-12

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Christopher J. Jezewski ,  Willy Rachmady ,  Rishabh Mehandru ,  Gilbert Dewey ,  Anh Phan

IPC: H01L21/8234 ,  H01L29/78

Abstract: In an embodiment of the present disclosure, a device structure includes a fin structure, a gate on the fin structure, and a source and a drain on the fin structure, where the gate is between the source and the drain. The device structure further includes an insulator layer having a first insulator layer portion adjacent to a sidewall of the source, a second insulator layer portion adjacent to a sidewall of the drain, and a third insulator layer portion therebetween adjacent to a sidewall of the gate, and two or more stressor materials adjacent to the insulator layer. The stressor materials can be tensile or compressively stressed and may strain a channel under the gate.

公开(公告)号：US11342432B2

公开(公告)日：2022-05-24

申请号：US16833184

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Cory Weber ,  Willy Rachmady ,  Varun Mishra

IPC: H01L29/423 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.

公开(公告)号：US11257929B2

公开(公告)日：2022-02-22

申请号：US15770463

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Rishabh Mehandru ,  Aaron D. Lilak

IPC: H01L27/00 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side. A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.

公开(公告)号：US11239236B2

公开(公告)日：2022-02-01

申请号：US16827566

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Ehren Mannebach ,  Patrick Morrow ,  Willy Rachmady

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/10

Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a first transistor strata. The first transistor strata comprises a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone. In an embodiment, the semiconductor device further comprises a second transistor strata over the first transistor strata. The second transistor strata comprises a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone.

公开(公告)号：US20210074704A1

公开(公告)日：2021-03-11

申请号：US16650155

申请日：2018-01-10

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Gilbert Dewey ,  Willy Rachmady ,  Patrick Morrow ,  Rishabh Mehandru

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/417

Abstract: An integrated circuit structure includes a first portion of a bottom semiconductor fin extending horizontally in a length direction and vertically in a height direction, a second portion of the bottom semiconductor fin extending horizontally in the length direction and vertically in the height direction, a top semiconductor fin extending horizontally in the length direction and vertically in the height direction, and an insulator region extending horizontally in the length direction to electrically insulate the first portion of the bottom semiconductor fin from the second portion of the bottom semiconductor fin. The insulator region further extends vertically in the height direction in vertical alignment with the top semiconductor fin. The insulator region includes at least one of an insulator material and an airgap. In an embodiment, the top semiconductor fin is associated with a transistor, and the insulator region is in vertical alignment with a gate electrode of the transistor.

公开(公告)号：US10937665B2

公开(公告)日：2021-03-02

申请号：US16327713

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Harold W. Kennel ,  Patrick Morrow ,  Rishabh Mehandru ,  Stephen M. Cea

IPC: H01L21/322 ,  H01L21/265 ,  H01L21/768 ,  H01L21/38 ,  H01L21/70 ,  H01L23/26

Abstract: Methods and apparatus for gettering impurities in semiconductors are disclosed. A disclosed example multilayered die includes a substrate material, a component layer below the substrate material, and an impurity attractant region disposed in the substrate material.

公开(公告)号：US10892335B2

公开(公告)日：2021-01-12

申请号：US16341010

申请日：2016-12-01

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Willy Rachmady ,  Gilbert W. Dewey ,  Aaron D. Lilak ,  Justin R. Weber ,  Harold W. Kennel ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Disclosed herein are tri-gate and all-around-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a channel material disposed over a substrate; a gate electrode of a first tri-gate or all-around-gate transistor, disposed over a first part of the channel material; and a gate electrode of a second tri-gate or all-around-gate transistor, disposed over a second part of the channel material. The transistor arrangement may further include a device isolation structure made of a fixed charge dielectric material disposed over a third part of the channel material, the third part being between the first part and the second part of the channel material.