Invention Grant
- Patent Title: Method and apparatus for controlling cache line storage in cache memory
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Application No.: US15857837Application Date: 2017-12-29
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Publication No.: US11237972B2Publication Date: 2022-02-01
- Inventor: David A. Roberts
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Faegre Drinker Biddle & Reath LLP
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F12/0846 ; G06F12/0862 ; G06F12/0815

Abstract:
A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls a refresh operation so that a data refresh does not occur for the clean data only banks or the refresh rate is reduced for the clean data only banks. Partitions that store dirty data can also store clean data; however, other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.
Public/Granted literature
- US20190205253A1 METHOD AND APPARATUS FOR CONTROLLING CACHE LINE STORAGE IN CACHE MEMORY Public/Granted day:2019-07-04
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