Invention Grant
- Patent Title: Vertical thin film transistors having self-aligned contacts
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Application No.: US16022494Application Date: 2018-06-28
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Publication No.: US11296229B2Publication Date: 2022-04-05
- Inventor: Abhishek A. Sharma , Yih Wang , Van H. Le , Jack T. Kavalieros , Tahir Ghani , Nazila Haratipour , Benjamin Chu-Kung , Seung Hoon Sung , Gilbert Dewey , Shriram Shivaraman , Matthew V. Metz
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L29/417 ; H01L29/423 ; H01L29/66 ; H01L29/49
Abstract:
Thin film transistors are described. An integrated circuit structure includes a first source or drain contact above a substrate. A gate stack pedestal is on the first source or drain contact, the gate stack pedestal including a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer. A channel material layer is over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact. Dielectric spacers are adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal. A second source or drain contact is over a portion of the channel material layer over the gate stack pedestal.
Public/Granted literature
- US20200006572A1 VERTICAL THIN FILM TRANSISTORS HAVING SELF-ALIGNED CONTACTS Public/Granted day:2020-01-02
Information query
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