Invention Grant
- Patent Title: Simultaneous and selective wide gap partitioning of via structures using plating resist
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Application No.: US17080524Application Date: 2020-10-26
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Publication No.: US11304311B2Publication Date: 2022-04-12
- Inventor: Shinichi Iketani , Drew Doblar
- Applicant: SANMINA CORPORATION
- Applicant Address: US CA San Jose
- Assignee: SANMINA CORPORATION
- Current Assignee: SANMINA CORPORATION
- Current Assignee Address: US CA San Jose
- Agency: Loza & Loza, LLP
- Agent Julio Loza
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H05K1/02 ; H05K3/42

Abstract:
A multilayer printed circuit board is provided having a first conductive layer and a first plating resist selectively positioned within the first conductive layer. A second plating resist may be selectively positioned within a second conductive layer. A through hole extends through the first plating resist in the first conductive layer and the second plating resist in the second conductive layer. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.
Public/Granted literature
- US20210153360A1 SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST Public/Granted day:2021-05-20
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