Invention Grant
- Patent Title: Techniques to improve translation lookaside buffer reach by leveraging idle resources
-
Application No.: US17008435Application Date: 2020-08-31
-
Publication No.: US11321241B2Publication Date: 2022-05-03
- Inventor: Jagadish B. Kotra , Michael W. LeBeane
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Volpe Koenig
- Main IPC: G06F12/1027
- IPC: G06F12/1027 ; G06F12/0862 ; G06F12/0891 ; G06F12/126 ; G06F12/0846

Abstract:
Techniques are disclosed for processing address translations. The techniques include detecting a first miss for a first address translation request for a first address translation in a first translation lookaside buffer, in response to the first miss, fetching the first address translation into the first translation lookaside buffer and evicting a second address translation from the translation lookaside buffer into an instruction cache or local data share memory, detecting a second miss for a second address translation request referencing the second address translation, in the first translation lookaside buffer, and in response to the second miss, fetching the second address translation from the instruction cache or the local data share memory.
Public/Granted literature
- US20220066946A1 TECHNIQUES TO IMPROVE TRANSLATION LOOKASIDE BUFFER REACH BY LEVERAGING IDLE RESOURCES Public/Granted day:2022-03-03
Information query
IPC分类: