Invention Grant
- Patent Title: Addressing cache slices in a last level cache
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Application No.: US17229641Application Date: 2021-04-13
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Publication No.: US11429534B2Publication Date: 2022-08-30
- Inventor: Prakash Bangalore Prabhakar , James M. Van Dyke , Kun Fang
- Applicant: NVIDIA Corp.
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA Corp.
- Current Assignee: NVIDIA Corp.
- Current Assignee Address: US CA Santa Clara
- Agency: Rowan TELS LLC
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F12/1009 ; G06T1/60

Abstract:
A system in having M memory controllers between a first memory and a second memory having N operative memory slices, where N and M are not evenly divisible, includes logic to operate the M memory controllers to linearly distribute addresses of the second memory across the N operative memory slices. The system may be utilized in commercial applications such as data centers, autonomous vehicles, and machine learning.
Public/Granted literature
- US20210255963A1 ADDRESSING CACHE SLICES IN A LAST LEVEL CACHE Public/Granted day:2021-08-19
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