公开(公告)号：US20210089465A1

公开(公告)日：2021-03-25

申请号：US16583012

申请日：2019-09-25

Applicant: NVIDIA Corp.

Inventor： Prakash Bangalore Prabhakar ,  James M. Van Dyke ,  Kun Fang

IPC: G06F12/1009 ,  G06T1/60

Abstract: An addressing scheme in systems utilizing a number of operative memory slices in a last level cache that is not evenly divisible by a number of memory channels utilizes the operative slices exposes the full last level cache bandwidth and capacity to data processing logic in a high-performance graphics system.

公开(公告)号：US11429534B2

公开(公告)日：2022-08-30

申请号：US17229641

申请日：2021-04-13

Applicant: NVIDIA Corp.

Inventor： Prakash Bangalore Prabhakar ,  James M. Van Dyke ,  Kun Fang

IPC: G06F12/10 ,  G06F12/1009 ,  G06T1/60

Abstract: A system in having M memory controllers between a first memory and a second memory having N operative memory slices, where N and M are not evenly divisible, includes logic to operate the M memory controllers to linearly distribute addresses of the second memory across the N operative memory slices. The system may be utilized in commercial applications such as data centers, autonomous vehicles, and machine learning.

公开(公告)号：US20210255963A1

公开(公告)日：2021-08-19

申请号：US17229641

申请日：2021-04-13

Applicant: NVIDIA Corp.

Inventor： Prakash Bangalore Prabhakar ,  James M. Van Dyke ,  Kun Fang

IPC: G06F12/1009 ,  G06T1/60

Abstract: “A system in having M memory controllers between a first memory and a second memory having N operative memory slices, where N and M are not evenly divisible, includes logic to operate the M memory controllers to linearly distribute addresses of the second memory across the N operative memory slices. The system may be utilized in commercial applications such as data centers, autonomous vehicles, and machine learning.”

公开(公告)号：US10983919B2

公开(公告)日：2021-04-20

申请号：US16583012

申请日：2019-09-25

Applicant: NVIDIA Corp.

Inventor： Prakash Bangalore Prabhakar ,  James M Van Dyke ,  Kun Fang

IPC: G06F12/10 ,  G06F12/1009 ,  G06T1/60

Abstract: An addressing scheme in systems utilizing a number of operative memory slices in a last level cache that is not evenly divisible by a number of memory channels utilizes the operative slices exposes the full last level cache bandwidth and capacity to data processing logic in a high-performance graphics system.