Invention Grant
- Patent Title: Apparatus and method for optimized tile-based rendering
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Application No.: US17072253Application Date: 2020-10-16
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Publication No.: US11551400B2Publication Date: 2023-01-10
- Inventor: Prasoonkumar Surti , Tomas G. Akenine-Moller , David J. Cowperthwaite , Kun Tian , Peter L. Doyle , Brent E. Insko , Adam T. Lake
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06T15/00
- IPC: G06T15/00 ; G06T1/20 ; G06T1/60 ; G06T15/40 ; G06T15/50

Abstract:
A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.
Public/Granted literature
- US20210035348A1 APPARATUS AND METHOD FOR OPTIMIZED TILE-BASED RENDERING Public/Granted day:2021-02-04
Information query
IPC分类:
G | 物理 |
G06 | 计算;推算或计数 |
G06T | 一般的图像数据处理或产生 |
G06T15/00 | 3D〔三维〕图像的加工 |