公开(公告)号：US10242494B2

公开(公告)日：2019-03-26

申请号：US15477016

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Devan Burke ,  Philip R. Laws ,  Subramanian Maiyuran ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Peter L. Doyle

IPC: G06F9/50 ,  G06T1/20 ,  G06T5/20 ,  G06T15/80

Abstract: An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.

公开(公告)号：US20180286110A1

公开(公告)日：2018-10-04

申请号：US15477002

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Peter L. Doyle

IPC: G06T15/40 ,  G06T1/20 ,  G06T17/05 ,  G06T19/00 ,  G06T19/20

Abstract: Systems, apparatuses and methods may provide for technology that optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry shader. More particularly, systems, apparatuses and methods may provide a way to generate, by a write out fixed-function stage, one or more bounding volumes based on geometry data, as inputs to one or more stages of the graphics pipeline. The systems, apparatuses and methods may compute multiple bounding volumes in parallel, and improve the gamer experience, and enable photorealistic renderings at full speed, (e.g., such as human skin and facial expressions) that render three-dimensional (3D) action more realistically.

公开(公告)号：US09600926B2

公开(公告)日：2017-03-21

申请号：US14570710

申请日：2014-12-15

Applicant: Intel Corporation

Inventor： Peter L. Doyle

IPC: G06T15/00 ,  G06T15/40 ,  G06T1/20

CPC classification number: G06T15/40 ,  G06T1/20 ,  G06T15/005

Abstract: An apparatus and method are described for decoupling visibility bins and render tile dimensions for tiled rendering. In one embodiment of the invention, a single visibility pass over the scene objects is performed and all the visibility bins are generated in parallel. This allows for high performance when the number of render tiles exceeds the number of visibility bins. The regions upon which visibility testing/recording is done is decoupled from the render tile regions in one embodiment of the invention. This allows a given visibility bin to map to multiple render tiles, thus allowing a fixed number of visibility bins to support any number of render tiles.

公开(公告)号：US12061831B2

公开(公告)日：2024-08-13

申请号：US18474361

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Sanjeev S. Jahagirdar ,  Balaji Vembu ,  Devan Burke ,  Philip R. Laws ,  Kamal Sinha ,  Abhishek R. Appu ,  Elmoustapha Ould-Ahmed-Vall ,  Peter L. Doyle ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Altug Koker

IPC: G09G5/391 ,  G06F3/01 ,  G06F3/0484 ,  G06F3/14 ,  G09G5/00

CPC classification number: G06F3/1438 ,  G06F3/013 ,  G06F3/0484 ,  G09G5/391 ,  G09G5/001 ,  G09G2340/0435 ,  G09G2352/00 ,  G09G2354/00 ,  G09G2360/08 ,  G09G2360/121

Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

公开(公告)号：US11816384B2

公开(公告)日：2023-11-14

申请号：US17959374

申请日：2022-10-04

Applicant: Intel Corporation

Inventor： Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Sanjeev S. Jahagirdar ,  Balaji Vembu ,  Devan Burke ,  Philip R. Laws ,  Kamal Sinha ,  Abhishek R. Appu ,  Elmoustapha Ould-Ahmed-Vall ,  Peter L. Doyle ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Altug Koker

IPC: G06F3/14 ,  G06F3/01 ,  G09G5/391 ,  G06F3/0484 ,  G09G5/00

CPC classification number: G06F3/1438 ,  G06F3/013 ,  G06F3/0484 ,  G09G5/391 ,  G09G5/001 ,  G09G2340/0435 ,  G09G2352/00 ,  G09G2354/00 ,  G09G2360/08 ,  G09G2360/121

Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

公开(公告)号：US20220076479A1

公开(公告)日：2022-03-10

申请号：US17400839

申请日：2021-08-12

Applicant: Intel Corporation

Inventor： Peter L. Doyle

IPC: G06T15/00 ,  G06T1/20 ,  G06F9/38 ,  G06F9/30

Abstract: Systems, apparatuses and methods may provide for technology that optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry shader. More particularly, systems, apparatuses and methods may provide a way to generate, by a write out fixed-function stage, one or more bounding volumes based on geometry data, as inputs to one or more stages of the graphics pipeline. The systems, apparatuses and methods may compute multiple bounding volumes in parallel, and improve the gamer experience, and enable photorealistic renderings at full speed, (e.g., such as human skin and facial expressions) that render three-dimensional (3D) action more realistically.

公开(公告)号：US20210357618A1

公开(公告)日：2021-11-18

申请号：US17221283

申请日：2021-04-02

Applicant: Intel Corporation

Inventor： Radhakrishnan Venkataraman ,  James M. Holland ,  Sayan Lahiri ,  Pattabhiraman K ,  Kamal Sinha ,  Chandrasekaran Sakthivel ,  Daniel Pohl ,  Vivek Tiwari ,  Philip R. Laws ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Peter L. Doyle ,  Devan Burke

IPC: G06K9/00 ,  G09G5/10 ,  G09G5/391 ,  G06F3/01 ,  G06F3/147 ,  G09G5/00 ,  G09G5/393 ,  G09G5/36

Abstract: Systems, apparatuses, and methods may provide for technology to dynamically control a display in response to ocular characteristic measurements of at least one eye of a user.

公开(公告)号：US10930060B2

公开(公告)日：2021-02-23

申请号：US16269270

申请日：2019-02-06

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Devan Burke ,  Philip R. Laws ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  Elmoustapha Ould-Ahmed-Vall ,  Peter L. Doyle

IPC: G06T15/80 ,  G06F9/50 ,  G06T1/20 ,  G06T5/20

Abstract: An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.

公开(公告)号：US20180286115A1

公开(公告)日：2018-10-04

申请号：US15477016

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Devan Burke ,  Philip R. Laws ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Peter L. Doyle

IPC: G06T15/80 ,  G06T5/20 ,  G06F9/50 ,  G06T1/20

CPC classification number: G06T15/80 ,  G06F9/50 ,  G06F9/5011 ,  G06T1/20 ,  G06T5/20

Abstract: An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.

公开(公告)号：US20170169539A1

公开(公告)日：2017-06-15

申请号：US15445852

申请日：2017-02-28

Applicant: INTEL CORPORATION

Inventor： Peter L. Doyle ,  Jeffery S. Boles ,  Arthur D. Hunter, JR. ,  Altug Koker ,  Aditya Navale

IPC: G06T1/60 ,  G06T15/00 ,  G06T15/10 ,  G06T1/20

CPC classification number: G06T15/10 ,  G06T11/40 ,  G06T15/005 ,  G06T2210/52

Abstract: Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.