Invention Grant
- Patent Title: High reliability fault tolerant computer architecture
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Application No.: US16536745Application Date: 2019-08-09
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Publication No.: US11586514B2Publication Date: 2023-02-21
- Inventor: Chester W. Pawlowski , John M. Chaves , Andrew Alden , Craig D. Keefer , Christopher D. Cotton , Michael Egan
- Applicant: STRATUS TECHNOLOGIES IRELAND LTD.
- Applicant Address: IE Dublin
- Assignee: STRATUS TECHNOLOGIES IRELAND LTD.
- Current Assignee: STRATUS TECHNOLOGIES IRELAND LTD.
- Current Assignee Address: IE Dublin
- Agency: K&L Gates LLP
- Main IPC: G06F11/20
- IPC: G06F11/20 ; G06F13/28 ; G06F13/40 ; G06F13/42

Abstract:
A fault tolerant computer system and method are disclosed. The system may include a plurality of CPU nodes, each including: a processor and a memory; at least two IO domains, wherein at least one of the IO domains is designated an active IO domain performing communication functions for the active CPU nodes; and a switching fabric connecting each CPU node to each IO domain. One CPU node is designated a standby CPU node and the remainder are designated as active CPU nodes. If a failure, a beginning of a failure, or a predicted failure occurs in an active node, the state and memory of the active CPU node are transferred to the standby CPU node which becomes the new active CPU node. If a failure occurs in an active IO domain, the communication functions performed by the failing active IO domain are transferred to the other IO domain.
Public/Granted literature
- US20200050523A1 HIGH RELIABILITY FAULT TOLERANT COMPUTER ARCHITECTURE Public/Granted day:2020-02-13
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