公开(公告)号：US20230185681A1

公开(公告)日：2023-06-15

申请号：US18106550

申请日：2023-02-07

Applicant: STRATUS TECHNOLOGIES IRELAND LTD.

Inventor： Chester W. Pawlowski ,  John M. Chaves ,  Andrew Alden ,  Craig D. Keefer ,  Christopher D. Cotton ,  Michael Egan

IPC: G06F11/20 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F11/2028 ,  G06F11/2007 ,  G06F11/203 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2201/82 ,  G06F2213/0026

Abstract: A fault tolerant computer system and method are disclosed. The system may include a plurality of CPU nodes, each including: a processor and a memory; at least two IO domains, wherein at least one of the IO domains is designated an active IO domain performing communication functions for the active CPU nodes; and a switching fabric connecting each CPU node to each IO domain. One CPU node is designated a standby CPU node and the remainder are designated as active CPU nodes. If a failure, a beginning of a failure, or a predicted failure occurs in an active node, the state and memory of the active CPU node are transferred to the standby CPU node which becomes the new active CPU node. If a failure occurs in an active IO domain, the communication functions performed by the failing active IO domain are transferred to the other IO domain.

公开(公告)号：US20240176739A1

公开(公告)日：2024-05-30

申请号：US18072297

申请日：2022-11-30

Applicant: STRATUS TECHNOLOGIES IRELAND LTD.

Inventor： Andrew Alden ,  Chester Pawlowski ,  Christopher Cotton ,  John Chaves

IPC: G06F12/0815 ,  G06F12/0891

CPC classification number: G06F12/0815 ,  G06F12/0891 ,  G06F2212/1032

Abstract: In part, the disclosure relates to a fault tolerant system. The system may include one or more shared memory complexes, each memory complex comprising a group of M computer-readable memory storage devices; one or more cache coherent switches comprising two or more host ports and one or more downstream device ports, the cache coherent switch in electrical communication with the one or more shared memory storage device; a first management processor in electrical communication with the cache coherent switch; a first compute node comprising a first processor and a first cache, the first compute node in electrical communication with the one or more cache coherent switches and the one or more shared memory complexes; a second compute node comprising a second processor and a second cache, the second compute node in electrical communication with the one or more cache coherent switches and the one or more shared memory complexes.

公开(公告)号：US11586514B2

公开(公告)日：2023-02-21

申请号：US16536745

申请日：2019-08-09

Applicant: STRATUS TECHNOLOGIES IRELAND LTD.

Inventor： Chester W. Pawlowski ,  John M. Chaves ,  Andrew Alden ,  Craig D. Keefer ,  Christopher D. Cotton ,  Michael Egan

IPC: G06F11/20 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

Abstract: A fault tolerant computer system and method are disclosed. The system may include a plurality of CPU nodes, each including: a processor and a memory; at least two IO domains, wherein at least one of the IO domains is designated an active IO domain performing communication functions for the active CPU nodes; and a switching fabric connecting each CPU node to each IO domain. One CPU node is designated a standby CPU node and the remainder are designated as active CPU nodes. If a failure, a beginning of a failure, or a predicted failure occurs in an active node, the state and memory of the active CPU node are transferred to the standby CPU node which becomes the new active CPU node. If a failure occurs in an active IO domain, the communication functions performed by the failing active IO domain are transferred to the other IO domain.