公开(公告)号：US20230185681A1

公开(公告)日：2023-06-15

申请号：US18106550

申请日：2023-02-07

Applicant: STRATUS TECHNOLOGIES IRELAND LTD.

Inventor： Chester W. Pawlowski ,  John M. Chaves ,  Andrew Alden ,  Craig D. Keefer ,  Christopher D. Cotton ,  Michael Egan

IPC: G06F11/20 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F11/2028 ,  G06F11/2007 ,  G06F11/203 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2201/82 ,  G06F2213/0026

Abstract: A fault tolerant computer system and method are disclosed. The system may include a plurality of CPU nodes, each including: a processor and a memory; at least two IO domains, wherein at least one of the IO domains is designated an active IO domain performing communication functions for the active CPU nodes; and a switching fabric connecting each CPU node to each IO domain. One CPU node is designated a standby CPU node and the remainder are designated as active CPU nodes. If a failure, a beginning of a failure, or a predicted failure occurs in an active node, the state and memory of the active CPU node are transferred to the standby CPU node which becomes the new active CPU node. If a failure occurs in an active IO domain, the communication functions performed by the failing active IO domain are transferred to the other IO domain.

公开(公告)号：US20250130721A1

公开(公告)日：2025-04-24

申请号：US18399469

申请日：2023-12-28

Applicant: STRATUS TECHNOLOGIES IRELAND LTD.

Inventor： Michael Egan ,  Beverly Brown ,  Lei Cao ,  Steven Haid ,  Charles Horvath

IPC: G06F3/06

Abstract: In part, in one aspect, the disclosure relates to a first computer system including a first processor and first memory, a first IO storage subsystem including a first switch configured for one or more first storage devices, a first IO non-storage subsystem including a first which configured for one or more first non-storage devices, a second compute system including a second processor and second memory, a second storage IO subsystem including a second switch configured for one or more second storage devices, a second IO non-storage subsystem including a second switch configured for one or more second non-storage devices and a midplane including a power connector, a processor side and an IO side, wherein the processing side includes connectors in electrical communication with the computer systems, the IO side includes connectors in electrical communication with the storage and non-storage subsystems.

公开(公告)号：US11586514B2

公开(公告)日：2023-02-21

申请号：US16536745

申请日：2019-08-09

Applicant: STRATUS TECHNOLOGIES IRELAND LTD.

Inventor： Chester W. Pawlowski ,  John M. Chaves ,  Andrew Alden ,  Craig D. Keefer ,  Christopher D. Cotton ,  Michael Egan

IPC: G06F11/20 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

Abstract: A fault tolerant computer system and method are disclosed. The system may include a plurality of CPU nodes, each including: a processor and a memory; at least two IO domains, wherein at least one of the IO domains is designated an active IO domain performing communication functions for the active CPU nodes; and a switching fabric connecting each CPU node to each IO domain. One CPU node is designated a standby CPU node and the remainder are designated as active CPU nodes. If a failure, a beginning of a failure, or a predicted failure occurs in an active node, the state and memory of the active CPU node are transferred to the standby CPU node which becomes the new active CPU node. If a failure occurs in an active IO domain, the communication functions performed by the failing active IO domain are transferred to the other IO domain.