Invention Grant
- Patent Title: Processed stacked dies
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Application No.: US17124306Application Date: 2020-12-16
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Publication No.: US11652083B2Publication Date: 2023-05-16
- Inventor: Cyprian Emeka Uzoh , Guilian Gao , Laura Wills Mirkarimi , Gaius Gillman Fountain, Jr.
- Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Applicant Address: US CA San Jose
- Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Current Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Current Assignee Address: US CA San Jose
- Agency: Knobbe, Martens, Olson & Bear, LLP
- The original application number of the division: US15960179 2018.04.23
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/308 ; H01L21/311 ; H01L21/683 ; H01L21/78 ; H01L23/31 ; H01L25/065 ; H01L25/00 ; H01L21/02 ; H01L21/3065

Abstract:
Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.
Public/Granted literature
- US20210104487A1 PROCESSED STACKED DIES Public/Granted day:2021-04-08
Information query
IPC分类: