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公开(公告)号：US20240404990A1
公开(公告)日：2024-12-05
申请号：US18783239
申请日：2024-07-24
IPC: H01L23/00 , H01L21/02 , H01L21/3065 , H01L21/308 , H01L21/311 , H01L21/683 , H01L21/78 , H01L23/31 , H01L25/00 , H01L25/065
Abstract: Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.
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公开(公告)号：US12132020B2
公开(公告)日：2024-10-29
申请号：US18539143
申请日：2023-12-13
Inventor： Cyprian Emeka Uzoh , Jeremy Alfred Theil , Rajesh Katkar , Guilian Gao , Laura Wills Mirkarimi
IPC: H01L23/00
CPC classification number: H01L24/08 , H01L24/80 , H01L2224/08057 , H01L2224/08147 , H01L2224/80895 , H01L2224/80896
Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
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公开(公告)号：US11978681B2
公开(公告)日：2024-05-07
申请号：US17825240
申请日：2022-05-26
Inventor： Guilian Gao , Laura Wills Mirkarimi , Gaius Gillman Fountain, Jr.
IPC: H01L21/66 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/538
CPC classification number: H01L22/34 , H01L21/7685 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L23/53266 , H01L23/5386
Abstract: Mitigating surface damage of probe pads in preparation for direct bonding of a substrate is provided. Methods and layer structures prepare a semiconductor substrate for direct bonding processes by restoring a flat direct-bonding surface after disruption of probe pad surfaces during test probing. An example method fills a sequence of metals and oxides over the disrupted probe pad surfaces and builds out a dielectric surface and interconnects for hybrid bonding. The interconnects may be connected to the probe pads, and/or to other electrical contacts of the substrate. A layer structure is described for increasing the yield and reliability of the resulting direct bonding process. Another example process builds the probe pads on a next-to-last metallization layer and then applies a direct bonding dielectric layer and damascene process without increasing the count of mask layers. Another example process and related layer structure recesses the probe pads to a lower metallization layer and allows recess cavities over the probe pads.
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公开(公告)号：US20240113059A1
公开(公告)日：2024-04-04
申请号：US18539143
申请日：2023-12-13
Inventor： Cyprian Emeka Uzoh , Jeremy Alfred Theil , Rajesh Katkar , Guilian Gao , Laura Wills Mirkarimi
IPC: H01L23/00
CPC classification number: H01L24/08 , H01L24/80 , H01L2224/08057 , H01L2224/08147 , H01L2224/80895 , H01L2224/80896
Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
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公开(公告)号：US20230268300A1
公开(公告)日：2023-08-24
申请号：US18173690
申请日：2023-02-23
Inventor： Cyprian Emeka Uzoh , Rajesh Katkar , Thomas Workman , Gaius Gillman Fountain, Jr. , Guilian Gao , Jeremy Alfred Theil , Gabriel Z. Guevara , Kyong-Mo Bang , Laura Wills Mirkarimi
IPC: H01L23/00 , H01L25/16 , H01L25/065 , H01L23/498 , H01L23/48
CPC classification number: H01L24/08 , H01L25/16 , H01L25/0657 , H01L25/0655 , H01L25/0652 , H01L23/49838 , H01L23/481 , H01L24/80 , H01L2224/80895 , H01L2224/80896 , H01L2225/06524 , H01L2225/06527 , H01L2924/1011 , H01L2924/1815 , H01L2924/182 , H01L2224/08145 , H01L2224/08121 , H01L2224/08225
Abstract: A bonded structure can include a carrier including a first conductive contact and a second conductive contact, a first singulated element including a third conductive contact directly bonded to the first conductive contact without an adhesive, and a second singulated element including a fourth conductive contact directly bonded to the second conductive contact without an adhesive, wherein the first and second conductive contacts are spaced apart by a contact spacing of no more than 250 microns.
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Patent Agency Ranking
公开(公告)号：US11728313B2
公开(公告)日：2023-08-15
申请号：US17246845
申请日：2021-05-03
Inventor： Bongsub Lee , Guilian Gao
IPC: H01L25/065 , H01L23/00 , H01L23/48 , H01L23/482 , H01L21/768 , H01L23/522
CPC classification number: H01L25/0657 , H01L21/76843 , H01L21/76895 , H01L23/481 , H01L23/4824 , H01L23/5226 , H01L24/09 , H01L24/32 , H01L24/80 , H01L24/83 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2225/06524 , H01L2225/06544
Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad may be disposed at a bonding surface of at least one of the microelectronic substrates, where the contact pad is positioned offset relative to a TSV in the substrate and electrically coupled to the TSV.
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公开(公告)号：US20230215836A1
公开(公告)日：2023-07-06
申请号：US18145607
申请日：2022-12-22
Inventor： Belgacem Haba , Rajesh Katkar , Guilian Gao , Cyprian Emeka Uzoh
IPC: H01L23/00
CPC classification number: H01L24/80 , H01L24/08 , H01L2224/08225 , H01L2224/80006 , H01L2224/80895 , H01L2224/80896
Abstract: A bonded structure with a package substrate comprising an inorganic, insulating first bonding layer and first conductive features at a surface thereof and an electronic component comprising an inorganic, insulating second bonding layer and second conductive features at a surface thereof wherein the first bonding layer and the second bonding layer are directly bonded to one another, and the first and second conductive features are directly bonded to one another.
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公开(公告)号：US20230197655A1
公开(公告)日：2023-06-22
申请号：US18068150
申请日：2022-12-19
Inventor： Jeremy Alfred Theil , Cyprian Emeka Uzoh , Guilian Gao
IPC: H01L23/00
CPC classification number: H01L24/08 , H01L24/05 , H01L2224/08145 , H01L2224/05583 , H01L2224/05582 , H01L2224/05647 , H01L2224/05686 , H01L2924/04941 , H01L2924/04953 , H01L2224/05681 , H01L2224/05693 , H01L2924/05432 , H01L2924/05042 , H01L2924/04642
Abstract: Methods for fabrication dielectric layers having conductive contact pads, and directly bonding the dielectric and conductive bonding surfaces of the dielectric layers. In some aspects, the method includes disposing a polish stop layer on dielectric bonding surfaces on top of a dielectric layer. A conductive layer is disposed on top of the polish stop layer and then polished to form conductive contact pads having polished conducting bonding surfaces. During the polishing process, the polish stop layer reduces rounding of dielectric edges and erosion of the dielectric bonding surfaces between closely spaced conductive bonding surfaces. The resulting polished dielectric and conductive bonding surfaces are directly bonded to dielectric and conductive bonding surfaces of another dielectric layer to form conductive interconnects.
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公开(公告)号：US20230187412A1
公开(公告)日：2023-06-15
申请号：US18048586
申请日：2022-10-21
Inventor： Guilian Gao , Gaius Gillman Fountain, JR. , Belgacem Haba
IPC: H01L25/065 , H01L23/00 , H01L25/00
CPC classification number: H01L25/0657 , H01L24/08 , H01L24/48 , H01L25/50 , H01L25/18
Abstract: A stacked electronic device is disclosed. The stacked electronic device can comprise a die stack including two or more connected dies, such as a lower die, an upper die, and a middle die between the lower die and the upper die. A plurality of through substrate vias (TSVs) can provide signal transmission to dies of the stack. A power supply path can be configured to provide power to the middle die without passing through the lower die. In some embodiments, external paths can provide power through an upper surface of a die in the stack while signals are supplied through the lower surface.
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10.发明申请公开(公告)号：US20230118156A1
公开(公告)日：2023-04-20
申请号：US18069485
申请日：2022-12-21
Inventor： Guilian Gao , Gaius Gillman Fountain, JR. , Laura Wills Mirkarimi , Rajesh Katkar , Ilyas Mohammed , Cyprian Emeka Uzoh
IPC: H01L23/00 , H01L23/522 , H01L21/768
Abstract: Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.
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