公开(公告)号：US20250006689A1

公开(公告)日：2025-01-02

申请号：US18513145

申请日：2023-11-17

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Gaius Gillman Fountain, JR. ,  Thomas Workman ,  Guilian Gao ,  Laura Wills Mirkarimi

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/768 ,  H01L25/065

Abstract: Disclosed is a bonded structure including a substrate that includes a surface and at least one bumper extending above the surface by a bumper height. The bonded structure further includes at least one die directly bonded to the surface adjacent the bumper.

公开(公告)号：US20250006679A1

公开(公告)日：2025-01-02

申请号：US18391173

申请日：2023-12-20

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Jeremy Alfred Theil ,  Cyprian Emeka Uzoh ,  Guilian Gao ,  Belgacem Haba ,  Laura Wills Mirkarimi

IPC: H01L23/00

Abstract: A structure includes a first substrate including a first layer having at least one electrically conductive first portion and at least one electrically insulative second portion and a second substrate including a second layer having at least one electrically conductive third portion and at least one electrically insulative fourth portion. The structure further includes an interface layer having at least one electrically conductive oxide material between the first layer and the second layer. The at least one electrically conductive oxide material includes at least one first region between and in electrical communication with the at least one electrically conductive first portion and the at least one electrically conductive third portion, and at least one second region between the at least one electrically insulative second portion and the at least one electrically insulative fourth portion.

公开(公告)号：US20240371850A1

公开(公告)日：2024-11-07

申请号：US18541869

申请日：2023-12-15

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi ,  Guilian Gao ,  Gaius Gillman Fountain, JR.

IPC: H01L25/00 ,  H01L21/18 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L25/065

Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

公开(公告)号：US20240312953A1

公开(公告)日：2024-09-19

申请号：US18671851

申请日：2024-05-22

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Guilian Gao ,  Laura Wills Mirkarimi ,  Gaius Gillman Fountain, JR. ,  Cyprian Emeka Uzoh

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/80031 ,  H01L2224/80143 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements. The differential expansion compensation structure can be configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.

公开(公告)号：US11955445B2

公开(公告)日：2024-04-09

申请号：US17836840

申请日：2022-06-09

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Guilian Gao ,  Bongsub Lee ,  Gaius Gillman Fountain, Jr. ,  Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L24/94 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/08146 ,  H01L2224/80896

Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

公开(公告)号：US20250125248A1

公开(公告)日：2025-04-17

申请号：US18782477

申请日：2024-07-24

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Rajesh Katkar ,  Gabriel Z. Guevara ,  Javier A. DeLaCruz ,  Shaowu Huang ,  Laura Wills Mirkarimi

IPC: H01L23/498 ,  H01G2/02 ,  H01G4/12 ,  H01G4/228 ,  H01G4/30 ,  H01G4/38 ,  H01G4/40 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/66 ,  H05K1/02 ,  H05K1/18

Abstract: In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.

公开(公告)号：US12136605B2

公开(公告)日：2024-11-05

申请号：US17320767

申请日：2021-05-14

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Guilian Gao ,  Gaius Gillman Fountain, Jr. ,  Laura Wills Mirkarimi ,  Rajesh Katkar ,  Ilyas Mohammed ,  Cyprian Emeka Uzoh

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/00

Abstract: Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.

公开(公告)号：US12100676B2

公开(公告)日：2024-09-24

申请号：US17559485

申请日：2021-12-22

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Jeremy Alfred Theil ,  Rajesh Katkar ,  Guilian Gao ,  Laura Wills Mirkarimi

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L2224/08057 ,  H01L2224/08147 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

公开(公告)号：US20240194625A1

公开(公告)日：2024-06-13

申请号：US18582312

申请日：2024-02-20

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Guilian Gao ,  Bongsub Lee ,  Gaius Gillman Fountain, JR. ,  Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L24/94 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/08146 ,  H01L2224/80896

Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

公开(公告)号：US11955393B2

公开(公告)日：2024-04-09

申请号：US17315170

申请日：2021-05-07

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Rajesh Katkar ,  Laura Wills Mirkarimi ,  Bongsub Lee ,  Gaius Gillman Fountain, Jr. ,  Cyprian Emeka Uzoh

IPC: H01L23/10 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/10 ,  H01L21/76807 ,  H01L21/76816 ,  H01L24/08 ,  H01L2924/01029

Abstract: A bonded structure is disclosed. The bonded structure includes a first element and a second element that is bonded to the first element along a bonding interface. The bonding interface has an elongate conductive interface feature and a nonconductive interface feature. The bonded structure also includes an integrated device that is coupled to or formed with the first element or the second element. The elongate conductive interface feature has a recess through a portion of a thickness of the elongate conductive interface feature. A portion of the nonconductive interface feature is disposed in the recess.