Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, determining that a value of a write counter associated with the memory device satisfies a first threshold criterion. The operations performed by the processing device further include, responsive to determining that the value of the write counter satisfies the first threshold criterion, identifying a first memory unit and a second memory unit of the memory device, the second memory unit comprising one or more memory cells adjacent to one or more memory cells of the first memory unit. The operations performed by the processing device further include performing a read operation on the second memory unit to determine a set of failed bit count statistics corresponding to a plurality of codewords of the second memory unit. The operations performed by the processing device further include determining that the set of failed bit count statistics corresponding to the plurality of codewords of the second memory unit satisfies a second threshold criterion. The operations performed by the processing device further include, responsive to determining that the set of failed bit count statistics corresponding to the plurality of codewords of the second memory unit satisfies the second threshold criterion, performing a write scrub operation on the second memory unit.