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    Managing the programming of an open translation unit
    1.
    发明授权
    Managing the programming of an open translation unit 有权

    公开(公告)号：US12217794B2

    公开(公告)日：2025-02-04

    申请号：US18425619

    申请日：2024-01-29

    Applicant: Micron Technology, Inc.

    Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Tingjun Xie ,  Jiangli Zhu ,  Nagendra Prasad Ganesh Rao ,  Sead Zildzic

    IPC: G11C11/56

    Abstract: A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.

    MANAGING ALLOCATION OF BLOCKS IN A MEMORY SUB-SYSTEM
    2.
    发明申请
    MANAGING ALLOCATION OF BLOCKS IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20250006269A1

    公开(公告)日：2025-01-02

    申请号：US18647554

    申请日：2024-04-26

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Zhenming Zhou ,  Shyam Sunder Raghunathan ,  Tingjun Xie

    IPC: G11C16/10 ,  G11C16/08

    Abstract: A processing device, operatively coupled with a memory device, receives a request to perform a programming operation on a first set of a block addressable by a first wordline of a first die of the memory device, wherein the first die comprises a plurality of decks of the memory device. The processing device identifies, based on a predefined usage type associated with the first die, a deck of the plurality of decks for performing the programming operation; and performing the programming operation on a second set of cells of the block addressable by the first wordline residing on the identified deck of the first die.

    Adjusting read-level thresholds based on write-to-write delay
    8.
    发明授权
    Adjusting read-level thresholds based on write-to-write delay 有权

    公开(公告)号：US11742029B2

    公开(公告)日：2023-08-29

    申请号：US17402279

    申请日：2021-08-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhongguang Xu ,  Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

    IPC: G11C16/30 ,  G11C16/26 ,  G11C16/10 ,  G11C16/34 ,  G11C16/32

    CPC classification number: G11C16/26 ,  G11C16/102 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3404

    Abstract: A method includes performing a first write operation that writes data to a first memory unit of a group of memory units in a memory device, determining a write-to-write (W2W) delay based on a time difference between the first write operation and a second write operation on a memory unit in the group of memory units, wherein the second write operation occurred prior to the first write operation, identifying a threshold time criterion that is satisfied by the W2W delay, identifying a first read voltage level associated with the threshold time criterion, and associating the first read voltage level with a second memory unit of the group of memory units. The second memory unit can be associated with a second read voltage level that satisfies a selection criterion based on a comparison of the second read voltage level to the first read voltage level.

    READ REFRESH VIA SIGNAL CALIBRATION FOR NON-VOLATILE MEMORIES
    10.
    发明申请
    READ REFRESH VIA SIGNAL CALIBRATION FOR NON-VOLATILE MEMORIES 有权

    公开(公告)号：US20230120838A1

    公开(公告)日：2023-04-20

    申请号：US18086580

    申请日：2022-12-21

    Applicant: Micron Technology, Inc.

    Inventor： Tingjun Xie ,  Zhenming Zhou ,  Zhenlei Shen ,  Chih-Kuo Kao

    IPC: G06F3/06 ,  G11C7/10

    Abstract: A processing device in a memory sub-system initiates read operations on each of a plurality of segments in a first region of the memory device during a first time interval, wherein at least a subset of the plurality of segments in the first region of the memory device are storing host data. The processing device further receives, as a result of at least one read operation, at least one data signal from a corresponding one of the plurality of segments in the first region of the memory device, and performs a signal calibration operation using the at least one data signal to synchronize one or more relevant signals with a reference clock signal used by the processing device.

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