公开(公告)号：US20250166708A1

公开(公告)日：2025-05-22

申请号：US19030458

申请日：2025-01-17

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Vivek Shivhare ,  Vinh Diep ,  Zhenming Zhou

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/32 ,  G11C29/52

Abstract: Methods, systems, and apparatuses include determining an operation type for an operation. A sensing time is elected using the operation type. The operation is executed using the sensing time.

公开(公告)号：US20250130731A1

公开(公告)日：2025-04-24

申请号：US18786100

申请日：2024-07-26

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Jun Wan ,  Zhenming Zhou ,  Ying Tai

IPC: G06F3/06

Abstract: Programming data in memory is described herein. An example apparatus includes an array of memory cells having a plurality of access lines to which the cells are coupled, and a processing device that performs a program operation on the array, including programming data to be stored in one page of cells of the array to the cells of the array coupled to a first one of the access lines, programming additional data to be stored in that page to the cells of the array coupled to a second one of the access lines adjacent to the first one of the access lines, sensing the data programmed to the cells of the array coupled to the first one of the access lines, and programming data to be stored in two pages of cells of the array to the cells of the array coupled to the first one of the access lines.

公开(公告)号：US20250118364A1

公开(公告)日：2025-04-10

申请号：US18988243

申请日：2024-12-19

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Tingjun Xie ,  Jiangli Zhu ,  Nagendra Prasad Ganesh Rao ,  Sead Zildzic

IPC: G11C11/56

Abstract: A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.

公开(公告)号：US20250111886A1

公开(公告)日：2025-04-03

申请号：US18979331

申请日：2024-12-12

Applicant: Micron Technology, Inc.

Inventor： Li-Te Chang ,  Murong Lang ,  Zhenming Zhou ,  Ting Luo

IPC: G11C29/52 ,  G11C29/00 ,  G11C29/50

Abstract: Methods, systems, and devices for read window management in a memory system are described. A memory system may determine, for a set of memory cells, a first value for a read window that is associated with a set of one or more threshold voltages each representing a different multi-bit value. The memory system may then use the first value for the read window to predict a second value for the read window. Based on the second value for the read window, the memory system may predict an error rate for the set of memory cells. The memory system may then set a value for an offset for a threshold voltage of the set of one or more threshold voltages based on the error rate.

公开(公告)号：US20250104779A1

公开(公告)日：2025-03-27

申请号：US18782517

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Ting Luo ,  Zhenming Zhou

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34

Abstract: Methods, systems, and devices for a ganged read operation for multiple sub-blocks are described. The method may include writing a respective first logic state to each memory cell of a set of memory portions and biasing a first word line and a second word line to a first voltage. In some examples, the first word line may correspond to a first memory portion and the second word line may correspond to a second memory portion. Further, the method may include applying a first read pulse to the first word line and a second read pulse to the second word line and reading a second logic state from one or more memory cells of the first memory portion and the second memory portion. Further, the method may include validating the write operation based on reading the second logic state from the memory cells of the first memory portion and the second memory portion.

公开(公告)号：US20250104772A1

公开(公告)日：2025-03-27

申请号：US18971520

申请日：2024-12-06

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Murong Lang ,  Fangfang Zhu ,  Jiangli Zhu ,  Zhenming Zhou

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32

Abstract: A method includes performing, over a time period, a quantity of write operations associated with a quad-level cell (QLC) memory block, determining the time period exceeds a threshold time, designating the QLC memory block as a bimodal, determining a voltage threshold level of a last successful read operation associated with the QLC memory block, and setting a read threshold level of at least a portion of the QLC memory block at the voltage threshold level of the last successful read operation.

公开(公告)号：US20250094063A1

公开(公告)日：2025-03-20

申请号：US18968924

申请日：2024-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yu-Chung Lien ,  Zhenming Zhou

IPC: G06F3/06

Abstract: A program command specifying new data to be programmed is received and partitioned into a plurality of data partitions. A wordline addressing a first set of memory cells to be programmed with a data partition of the plurality of data partitions is identified for a specified block of the memory device. Existing data stored by a second set of memory cells is read. An expected data state metrics is produced for each data partition of the plurality of data partitions. A data partition associated with a lowest expected data state metric among the plurality of expected data state metrics is identified. The identified data partition is programmed to the identified wordline.

公开(公告)号：US12237003B2

公开(公告)日：2025-02-25

申请号：US17881180

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Zhenming Zhou

IPC: G11C16/04 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096

Abstract: A memory subsystem receives a first read command and a second read command. Responsive to determining that the first read command originated from a host system, the memory subsystem selects a reverse read trim setting. Responsive to determining that the second read command did not originate from the host system, the memory subsystem selects a forward read trim setting. The memory subsystem executes the first read command using the reverse read trim setting. The memory subsystem executes the second read command using the forward read trim setting.

公开(公告)号：US12216529B2

公开(公告)日：2025-02-04

申请号：US17933443

申请日：2022-09-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jian Huang ,  Zhenming Zhou ,  Zhongguang Xu ,  Murong Lang

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  G11C16/26 ,  G11C16/04

Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.

公开(公告)号：US20250006270A1

公开(公告)日：2025-01-02

申请号：US18753662

申请日：2024-06-25

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Aaron Lee ,  Zhenming Zhou

IPC: G11C16/10 ,  G11C16/08 ,  G11C29/52

Abstract: A processing device, operatively coupled with a memory device, performs a first programming operation on a first set of cells addressable by a first wordline of a first plane of the memory device. The processing device identifies a predefined index shift value associated with the first wordline. The processing device determines, by applying the predefined index shift value to a first index value of the first wordline, a second index value of a second wordline of a second plane of the memory device. The processing device further performs a second programming operation on a second set of cells addressable by the second wordline of the second plane.