Invention Grant
- Patent Title: Thin film transistor with charge trap layer
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Application No.: US16633603Application Date: 2017-09-27
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Publication No.: US11658222B2Publication Date: 2023-05-23
- Inventor: Abhishek A. Sharma , Van H. Le , Jack T. Kavalieros , Tahir Ghani , Gilbert Dewey , Shriram Shivaraman , Sean T. Ma , Benjamin Chu-Kung
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- International Application: PCT/US2017/053588 2017.09.27
- International Announcement: WO2019/066790A 2019.04.04
- Date entered country: 2020-01-24
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L29/40 ; H01L29/51 ; H01L21/28 ; H01L29/66 ; H01L29/786

Abstract:
An embodiment includes an apparatus comprising: a substrate; a thin film transistor (TFT) comprising: source, drain, and gate contacts; a semiconductor material, comprising a channel, between the substrate and the gate contact; a gate dielectric layer between the gate contact and the channel; and an additional layer between the channel and the substrate; wherein (a)(i) the channel includes carriers selected from the group consisting of hole carriers or electron carriers, (a)(ii) the additional layer includes an insulator material that includes charged particles having a polarity equal to a polarity of the carriers. Other embodiments are described herein.
Public/Granted literature
- US20200185504A1 THIN FILM TRANSISTOR WITH CHARGE TRAP LAYER Public/Granted day:2020-06-11
Information query
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