Double cross-couple for two-row flip-flop using CFET
Abstract:
A semiconductor device includes a cell array having tracks and rows formed on a substrate. The tracks extend perpendicularly to the rows. A logic cell is formed across two adjacent rows within the cell array. The logic cell includes a cross-couple (XC) in each row and a plurality of poly tracks across the two adjacent rows. Each XC includes two cross-coupled complementary field-effect-transistors. Each poly track is configured to function as an inter-row gate for the XCs. A pair of signal tracks is positioned on opposing boundaries of the logic cell and electrically coupled to the plurality of poly tracks.
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