公开(公告)号：US20250120174A1

公开(公告)日：2025-04-10

申请号：US18989404

申请日：2024-12-20

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Daniel Chanemougame ,  Paul Gutwin

IPC: H10D84/85 ,  H10D30/62 ,  H10D30/67 ,  H10D64/27 ,  H10D88/00

Abstract: A semiconductor device includes a first three dimensional (3D) transistor and a second 3D transistor oriented parallel to the first 3D transistor disposed in a substrate, the first 3D transistor and the second 3D transistor being a subset of a plurality of transistors. The device includes a diffusion-break trench disposed in a region laterally separating the second 3D transistor from the first 3D transistor, the diffusion-break trench having a length extending along a lateral direction. The device includes a diffusion-break wire filling the diffusion-break trench, the diffusion-break wire having a height along a vertical direction, gates of the plurality of transistors being made of a different conductive material than the diffusion-break wire.

公开(公告)号：US12237333B2

公开(公告)日：2025-02-25

申请号：US17222495

申请日：2021-04-05

Applicant: Tokyo Electron Limited

Inventor： Daniel Chanemougame ,  Lars Liebmann ,  Jeffrey Smith

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: A first transistor tier is formed over a substrate, positioned in a first tier of the semiconductor device and includes bottom transistors extending along a horizontal direction parallel to the substrate. A first segment of a first conductive plane is formed in the first tier and adjacent to a first side of the first transistor tier, spans a height of the first transistor tier, and is connected to the first transistor tier. A second transistor tier is formed over the first transistor tier, positioned in a second tier of the semiconductor device and includes top transistors extending along the horizontal direction. A second segment of the first conductive plane is formed in the second tier and adjacent to a first side of the second transistor tier, positioned over and connected to the first segment of the first conductive plane, and spans a height of the second transistor tier.

公开(公告)号：US12224281B2

公开(公告)日：2025-02-11

申请号：US17541609

申请日：2021-12-03

Applicant: TOKYO ELECTRON LIMITED

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Daniel Chanemougame ,  Paul Gutwin ,  Brian Cline ,  Xiaoqing Xu ,  David Pietromonaco

IPC: H01L27/06 ,  H01L27/092

Abstract: A semiconductor device includes a first pair of transistors over a substrate. The first pair of transistors includes a first transistor having a first gate structure over the substrate and a second transistor having a second gate structure stacked over the first transistor. A second pair of transistors is stacked over the first pair of transistors, resulting in a vertical stack perpendicular to a working surface of the substrate. The second pair of transistors includes a third transistor having a third gate structure stacked over the second transistor and a fourth transistor having a fourth gate structure stacked over the third transistor. The third gate structure extends from a central region of the vertical stack to a first side of the vertical stack. The second gate structure and the fourth gate structure extend from the central region to a second side of the vertical stack opposite the first side.

公开(公告)号：US12218135B2

公开(公告)日：2025-02-04

申请号：US17647938

申请日：2022-01-13

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Daniel Chanemougame ,  Paul Gutwin

IPC: H01L27/092 ,  H01L27/06 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device includes a first three dimensional (3D) transistor and a second 3D transistor oriented parallel to the first 3D transistor disposed in a substrate, the first 3D transistor and the second 3D transistor being a subset of a plurality of transistors. The device includes a diffusion-break trench disposed in a region laterally separating the second 3D transistor from the first 3D transistor, the diffusion-break trench having a length extending along a lateral direction. The device includes a diffusion-break wire filling the diffusion-break trench, the diffusion-break wire having a height along a vertical direction, gates of the plurality of transistors being made of a different conductive material than the diffusion-break wire.

公开(公告)号：US12218066B2

公开(公告)日：2025-02-04

申请号：US18458591

申请日：2023-08-30

Applicant: Tokyo Electron Limited

Inventor： Daniel Chanemougame ,  Lars Liebmann ,  Jeffrey Smith

IPC: H01L23/538 ,  H01L21/48 ,  H01L27/092

Abstract: An additional set of interconnects is created in bulk material, allowing connections to active devices to be made from both above and below. The interconnects below the active devices can form a power distribution network, and the interconnects above the active devices can form a signaling network. Various accommodations can be made to suit different applications, such as encapsulating buried elements, using sacrificial material, and replacing the bulk material with a dielectric. Epitaxial material can be used throughout the formation process, allowing for the creation of a monolithic substrate.

公开(公告)号：US11791271B2

公开(公告)日：2023-10-17

申请号：US17306331

申请日：2021-05-03

Applicant: Tokyo Electron Limited

Inventor： Daniel Chanemougame ,  Lars Liebmann ,  Jeffrey Smith

IPC: H01L23/538 ,  H01L21/48 ,  H01L27/092

CPC classification number: H01L23/5383 ,  H01L21/4885 ,  H01L27/0924

Abstract: An additional set of interconnects is created in bulk material, allowing connections to active devices to be made from both above and below. The interconnects below the active devices can form a power distribution network, and the interconnects above the active devices can form a signaling network. Various accommodations can be made to suit different applications, such as encapsulating buried elements, using sacrificial material, and replacing the bulk material with a dielectric. Epitaxial material can be used throughout the formation process, allowing for the creation of a monolithic substrate.

公开(公告)号：US11735525B2

公开(公告)日：2023-08-22

申请号：US16659251

申请日：2019-10-21

Applicant: TOKYO ELECTRON LIMITED

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton Devilliers ,  Daniel Chanemougame

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283

Abstract: A semiconductor device includes a first power rail, a first power input structure, a circuit and a first middle-of-line rail. The first power rail is formed in a first rail opening within a first isolation trench on a substrate. The first power input structure is configured to connect with a first terminal of a power source that is external of the semiconductor device to receive electrical power from the power source. The circuit is formed, on the substrate, by layers between the first power rail and the first power input structure. The first middle-of-line rail is formed by one or more of the layers that form the circuit. The first middle-of-line rail is configured to deliver the electrical power from the first power input structure to the first power rail, and the first power rail provides the electrical power to the circuit for operation.

公开(公告)号：US11631671B2

公开(公告)日：2023-04-18

申请号：US17136820

申请日：2020-12-29

Applicant: Tokyo Electron Limited

Inventor： H. Jim Fulford ,  Anton J. Devilliers ,  Mark I. Gardner ,  Daniel Chanemougame ,  Jeffrey Smith ,  Lars Liebmann ,  Subhadeep Kal

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/16 ,  H01L21/8238

Abstract: A method of fabricating a semiconductor device is provided. An initial stack of layers is formed over a substrate. The initial stack alternates between a first material layer and a second material layer that has a different composition from the first material layer. The initial stack is divided into a first stack and a second stack. First GAA transistors are formed in the first stack by using the first material layers as respective channel regions for the first GAA transistors and using the second material layers as respective replacement gates for the first GAA transistors. Second GAA transistors are formed in the second stack by using the second material layers as respective channel regions for the second GAA transistors and using the first material layers as respective replacement gates for the second GAA transistors. The second GAA transistors are vertically offset from the first GAA transistors.

公开(公告)号：US11495540B2

公开(公告)日：2022-11-08

申请号：US16660448

申请日：2019-10-22

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton deVilliers

IPC: H01L23/528 ,  H01L27/092 ,  H01L21/768 ,  H01L25/07

Abstract: Aspects of the disclosure provide a semiconductor apparatus including a plurality of structures. A first one of the structures comprises a first stack of transistors that includes a first transistor formed on a substrate and a second transistor stacked on the first transistor along a Z direction substantially perpendicular to a substrate plane of the semiconductor apparatus. The first one of the structures further includes local interconnect structures. The first transistor is sandwiched between two of the local interconnect structures. The first one of the structures further includes vertical conductive structures substantially parallel to the Z direction. The vertical conductive structures are configured to provide at least power supplies for the first one of the structures by electrically coupling with the local interconnect structures. A height of one of the vertical conductive structures along the Z direction is at least a height of the first one of the structures.

公开(公告)号：US11217583B2

公开(公告)日：2022-01-04

申请号：US16560490

申请日：2019-09-04

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton J. deVilliers ,  Kandabara Tapily

IPC: H01L27/092 ,  H01L29/423 ,  H01L23/535 ,  H01L29/417 ,  H01L23/528 ,  H01L29/08 ,  H01L21/3213 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/768 ,  H03K19/0948 ,  H01L27/02 ,  H01L29/10

Abstract: A semiconductor device is provided. The device includes a plurality of transistor pairs that are stacked over a substrate. Each of the plurality of transistor pairs includes a n-type transistor and a p-type transistor that are stacked over one another. The device also includes a plurality of gate electrodes that are stacked over the substrate with a staircase configuration. The plurality of gate electrodes are electrically coupled to gate structures of the plurality of transistor pairs. The device further includes a plurality of source/drain (S/D) local interconnects that are stacked over the substrate with a staircase configuration. The plurality of S/D local interconnects are electrically coupled to source regions and drain regions of the plurality of transistor pairs.