Invention Grant
- Patent Title: Printed circuit board for galvanic effect reduction
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Application No.: US17715673Application Date: 2022-04-07
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Publication No.: US11924964B2Publication Date: 2024-03-05
- Inventor: Lin Hui Chen , Songtao Lu , Chien Te Chen , Yu Ying Tan , Huang Pao Yi , Ching Chuan Hsieh , T. Sharanya Kaminda , Chia-Hsuan Huang
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Michael Best & Friedrich LLP
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H05K1/02

Abstract:
Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.
Public/Granted literature
- US20230328873A1 PRINTED CIRCUIT BOARD FOR GALVANIC EFFECT REDUCTION Public/Granted day:2023-10-12
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