公开(公告)号：US12193166B2

公开(公告)日：2025-01-07

申请号：US17719815

申请日：2022-04-13

Applicant: Western Digital Technologies, Inc.

Inventor： Songtao Lu ,  Hsiang Ju Huang ,  Binbin Zheng ,  Cheng-Hsiung Yang ,  Chien-Te Chen

IPC: H05K3/28 ,  H05K1/09

Abstract: In one example, the present application describes a Printed Circuit Board (PCB) that mitigates galvanic corrosion during an Organic Solderability Preservative (OSP) process used during fabrication of the PCB. The PCB includes a first metal pattern and a second metal pattern electrically coupled to each other, where the first and second metal patterns are different metals. The first metal pattern has a first area that is exposed by a solder mask layer, and the second metal pattern has a second area that is exposed by the solder mask area. A ratio of the first area to the second area is less than a threshold ratio to mitigate the galvanic corrosion of the second metal pattern exposed on the PCB during the OSP process.

公开(公告)号：US20200006212A1

公开(公告)日：2020-01-02

申请号：US16277244

申请日：2019-02-15

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Rui Guo ,  Songtao Lu ,  Shenghua Huang ,  Ting Liu ,  Chin-Tien Chiu

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

Abstract: A substrate is disclosed having a stress relief layer. The stress relief layer may be applied to a dielectric core of the substrate, beneath a conductive layer in which electrical traces and contact pads are formed. The substrate including the stress relief layer may be incorporated into a semiconductor product which may, for example, be mounted on a host printed circuit board using solder balls on a surface of the substrate. The stress relief layer helps dissipate stresses within the substrate and improves the board level reliability.

公开(公告)号：US11234327B1

公开(公告)日：2022-01-25

申请号：US17214215

申请日：2021-03-26

Applicant: Western Digital Technologies, Inc.

Inventor： Songtao Lu ,  Cheng-Hsiung Yang ,  Yuequan Shi ,  Ye Bai ,  Chih-Chin Liao ,  JinXiang Huang

IPC: H05K1/02 ,  H05K3/00

Abstract: Devices and methods are described for reducing etching due to galvanic effect within a printed circuit board that may be used, for example, in a data storage device, such as a card-type data storage device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trance, and that is configured to couple the data storage device to a host device. The contact trace is electrically isolated from the rest of the circuitry during a fabrication process. The contact finger and an exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to an impedance trace though at least one of a component and a bond wire.

公开(公告)号：US11924964B2

公开(公告)日：2024-03-05

申请号：US17715673

申请日：2022-04-07

Applicant: Western Digital Technologies, Inc.

Inventor： Lin Hui Chen ,  Songtao Lu ,  Chien Te Chen ,  Yu Ying Tan ,  Huang Pao Yi ,  Ching Chuan Hsieh ,  T. Sharanya Kaminda ,  Chia-Hsuan Huang

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/0218 ,  H05K1/116 ,  H05K2201/09381 ,  H05K2201/0939

Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.

公开(公告)号：US20230337372A1

公开(公告)日：2023-10-19

申请号：US17719815

申请日：2022-04-13

Applicant: Western Digital Technologies, Inc.

Inventor： Songtao Lu ,  Hsiang Ju Huang ,  Binbin Zheng ,  Cheng-Hsiung Yang ,  Chien-Te Chen

IPC: H05K3/28 ,  H05K1/09

CPC classification number: H05K3/282 ,  H05K1/09 ,  H05K2203/0591

Abstract: In one example, the present application describes a Printed Circuit Board (PCB) that mitigates galvanic corrosion during an Organic Solderability Preservative (OSP) process used during fabrication of the PCB. The PCB includes a first metal pattern and a second metal pattern electrically coupled to each other, where the first and second metal patterns are different metals. The first metal pattern has a first area that is exposed by a solder mask layer, and the second metal pattern has a second area that is exposed by the solder mask area. A ratio of the first area to the second area is less than a threshold ratio to mitigate the galvanic corrosion of the second metal pattern exposed on the PCB during the OSP process.

公开(公告)号：US20230328873A1

公开(公告)日：2023-10-12

申请号：US17715673

申请日：2022-04-07

Applicant: Western Digital Technologies, Inc.

Inventor： Lin Hui Chen ,  Songtao Lu ,  Chien Te Chen ,  Yu Ying Tan ,  Huang Pao Yi ,  Ching Chuan Hsieh ,  T. Sharanya Kaminda ,  Chia-Hsuan Huang

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0218 ,  H05K1/116 ,  H05K2201/09381 ,  H05K2201/0939

Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.

公开(公告)号：US20230402361A1

公开(公告)日：2023-12-14

申请号：US17840322

申请日：2022-06-14

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Shenghua Huang ,  Binbin Zheng ,  Shaopeng Dong ,  Songtao Lu ,  Rui Guo ,  Yangming Liu ,  Bo Yang ,  Ning Ye

IPC: H01L23/498 ,  H01L23/12 ,  H01L23/31 ,  H01L25/065 ,  G06K19/077 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/12 ,  H01L23/3107 ,  H01L25/0657 ,  G06K19/07732 ,  H01L24/48 ,  H01L2225/06562 ,  H01L2924/3512 ,  H01L2924/1511 ,  H01L2224/48135

Abstract: A semiconductor device includes a substrate, semiconductor dies on the substrate, molding compound and reinforcing blocks on the substrate. The reinforcing blocks may be provided at positions on the substrate where mechanical stresses develop in the device during singulation, such as at curves and/or discontinuous points around the outline of the substrate, to add strength to the substrate.