公开(公告)号：US11924964B2

公开(公告)日：2024-03-05

申请号：US17715673

申请日：2022-04-07

Applicant: Western Digital Technologies, Inc.

Inventor： Lin Hui Chen ,  Songtao Lu ,  Chien Te Chen ,  Yu Ying Tan ,  Huang Pao Yi ,  Ching Chuan Hsieh ,  T. Sharanya Kaminda ,  Chia-Hsuan Huang

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/0218 ,  H05K1/116 ,  H05K2201/09381 ,  H05K2201/0939

Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.

公开(公告)号：US20230328873A1

公开(公告)日：2023-10-12

申请号：US17715673

申请日：2022-04-07

Applicant: Western Digital Technologies, Inc.

Inventor： Lin Hui Chen ,  Songtao Lu ,  Chien Te Chen ,  Yu Ying Tan ,  Huang Pao Yi ,  Ching Chuan Hsieh ,  T. Sharanya Kaminda ,  Chia-Hsuan Huang

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0218 ,  H05K1/116 ,  H05K2201/09381 ,  H05K2201/0939

Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.